Patents by Inventor Hong Du
Hong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090048333Abstract: The present invention provides compounds, pharmaceutical compositions and methods for the treatment of specific cancers. Such compositions may generally comprise a compound of formula (I): wherein R3-R6, R8-R10, R13 and Y are as defined herein, or pharmaceutically acceptable salts or esters thereof; and a pharmaceutically acceptable carrier.Type: ApplicationFiled: July 25, 2008Publication date: February 19, 2009Applicant: EISAI CO., LTD.Inventors: Hong Du, John (Yuan) Wang
-
Publication number: 20090024967Abstract: Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method also includes determining one or more characteristics of the reticle features of the simulated images. In addition, the method includes comparing the one or more characteristics of the reticle features of the simulated images to one or more characteristics of the reticle features printed on the wafer using a lithography process. The method further includes selecting one of the different generated models as the model to be used for predicting the printability of the reticle features based on results of the comparing step.Type: ApplicationFiled: May 6, 2008Publication date: January 22, 2009Inventors: Bo Su, Gaurav Verma, Hong Du, Rui-fang Shi, Scott Andrews
-
Patent number: 7413990Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).Type: GrantFiled: June 12, 2006Date of Patent: August 19, 2008Assignee: Applied Materials, Inc.Inventors: Yan Ye, Xiaoye Zhao, Hong Du
-
Patent number: 7313010Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: June 23, 2006Date of Patent: December 25, 2007Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
-
Publication number: 20070264249Abstract: The present invention comprises a method to diminish and/or eliminate atherosclerotic plaques, in mammals, through direct and indirect treatment of these plaques, in situ, using suitable substances which are capable of lipid removal, primarily through hydrolysis, either by a catalytic or stoichiometric process, wherein the substance targets receptors in and/or on the cell which lead to uptake into the lysosome. Such substances used to diminish and/or eliminate atherosclerotic plaques are generally comprised of lipid hydrolyzing proteins and/or polypeptides.Type: ApplicationFiled: January 12, 2007Publication date: November 15, 2007Inventors: Gregory Grabowski, Hong Du
-
Publication number: 20070253166Abstract: A lamp base assembly with electronic ballast for energy-saving lamp includes a housing (22), a lamp cap (21) and an electronic ballast (24) with transistors (23) provided within the housing. A transistor heat-diffusing element surrounding each transistor is provided within the lamp base, for enhancing the heat transfer from the transistors to the housing or the lamp cap, so that the heat generated from the transistors could be transferred out of the lamp base assembly. Thus, the heat-diffusing ability of the transistors is improved, and the working temperature of the transistors could be kept within a safe scope, so that the lifetime of the energy-saving lamp is guaranteed.Type: ApplicationFiled: November 11, 2005Publication date: November 1, 2007Applicant: PATENT-TREUHAND-GESELLSCHAFT FUR ELEKTRISCHE GLUHLAMPEN MBHInventors: Lai Qian Cen, Chao Hong Du, Wolfgang Pabst
-
Patent number: 7271744Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: December 14, 2006Date of Patent: September 18, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
-
Patent number: 7233194Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.Type: GrantFiled: October 9, 2003Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus
-
Patent number: 7176824Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: November 21, 2003Date of Patent: February 13, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
-
Patent number: 7153111Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.Type: GrantFiled: December 2, 2002Date of Patent: December 26, 2006Assignee: Carrier CorporationInventors: James W. Bush, Clark V. Cooper, Ronald T. Drost, Hong Du, Harry E. Eaton, Hussein E. Khalifa, Keshava B. Kumar, Reng Rong Lin, Philip H. McCluskey, Paula R. DeBlois, legal representative, Raymond DeBlois, deceased
-
Patent number: 7142627Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: GrantFiled: March 17, 2005Date of Patent: November 28, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
-
Publication number: 20060245286Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: June 23, 2006Publication date: November 2, 2006Inventors: Shan SUN, Xiao-Hong Du, Fan Chu, Bob Sommervold
-
Publication number: 20060247448Abstract: The present invention provides compounds having formula (I): and additionally provides methods for the synthesis thereof and methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein.Type: ApplicationFiled: March 7, 2003Publication date: November 2, 2006Applicant: Eisai Co., Ltd.Inventors: Roch Boivin, Kenichi Chiba, Jesse Chow, Hong Du, Yoshihito Eguchi, Masanori Fujita, Masaki Goto, Fabian Gusovsky, Jean-Christophe Harmanage, Atsushi Inoue, Yimin Jiang, Megumi Kawada, Takatoshi Kawai, Yoshiyuki Kawakami, Akifumi Kimura, Makoto Kotake, Yoshikazu Kuboi, Charles-Andre Lemelin, Xiang-Yi Li, Tomohiro Matsushima, Yoshiharu Mizui, Kenzo Muramoto, Hideki Sakurai, Yong-Chun Shen, Hiroshi Shirota, Mark Spyvee, Isao Tanaka, John Wang, Satoshi Yamamoto, Naoki Yoneda
-
Patent number: 7120220Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: GrantFiled: December 23, 2004Date of Patent: October 10, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
-
Patent number: 7116572Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: November 9, 2004Date of Patent: October 3, 2006Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
-
Patent number: 7115517Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).Type: GrantFiled: September 29, 2003Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Yan Ye, Xiaoye Zhao, Hong Du
-
Publication number: 20060216926Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).Type: ApplicationFiled: June 12, 2006Publication date: September 28, 2006Applicant: Applied Materials, Inc.Inventors: Yan Ye, Xiaoye Zhao, Hong Du
-
Publication number: 20060140331Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: ApplicationFiled: December 23, 2004Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
-
Publication number: 20060140332Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: ApplicationFiled: March 17, 2005Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
-
Publication number: 20060098470Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: November 9, 2004Publication date: May 11, 2006Inventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold