Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is deposited on the surface of the bores coacting with the rotors.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

Abstract: The present invention comprises a method to diminish and/or eliminate atherosclerotic plaques, in mammals, through direct and indirect treatment of these plaques, in situ, using suitable substances which are capable of lipid removal, primarily through hydrolysis, either by a catalytic or stoichiometric process, wherein the substance targets receptors in and/or on the cell which lead to uptake into the lysosome. Such substances used to diminish and/or eliminate atherosclerotic plaques are generally comprised of lipid hydrolyzing proteins and/or polypeptides.

Abstract: The present invention provides compositions comprising compounds having formula (I): 1

Abstract: The present invention comprises a method to diminish and/or eliminate atherosclerotic plaques, in mammals, through direct and indirect treatment of these plaques, in situ, using suitable substances which are capable of lipid removal, primarily through hydrolysis, either by a catalytic or stoichiometric process, wherein the substance targets receptors in and/or on the cell which lead to uptake into the lysosome. Such substances used to diminish and/or eliminate atherosclerotic plaques are generally comprised of lipid hydrolyzing proteins and/or polypeptides.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: A bit-line shielding technique for a ferroelectric memory logically divides the bit-lines in the array into two groups. When the bit-lines in one of the groups are accessed, the bit-lines in the other group are not accessed and thus can be grounded to electrically shield the bit-lines being accessed. Each group of bit-lines is coupled to the drains of a group of pre-charge devices at the bottom of the array. The sources of the pre-charge devices are grounded. The word lines are arranged so that only the bit-lines in one of the groups are accessed at a time.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: The present invention includes a method for patterning a bilayer resist having a patterned upper resist layer over a lower resist layer formed on a substrate. In one embodiment of the present invention, the method includes an optional upper resist layer trimming step, an upper resist layer treatment step, and a lower resist layer etching step. In the upper resist layer trimming step, the upper resist layer is trimmed in a plasma of a first process gas. In the upper resist layer treatment step, the upper resist layer is treated in a plasma of a second process gas to increase its etch resistance during the subsequent lower resist layer etching step. In the lower resist etching step, the lower resist layer is etched in a plasma of a third process gas, using the upper resist layer as a mask.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.

Abstract: The present invention comprises a method to diminish and/or eliminate atherosclerotic plaques, in mammals, through direct and indirect treatment of these plaques, in situ, using suitable substances which are capable of lipid removal, primarily through hydrolysis, either by a catalytic or stoichiometric process, wherein the substance targets receptors in and/or on the cell which lead to uptake into the lysosome. Such substances used to diminish and/or eliminate atherosclerotic plaques are generally comprised of lipid hydrolyzing proteins and/or polypeptides.

Abstract: A screw machine (10) has a rotor housing (12) defining overlapping bores (12-1, 12-2). Female rotor (14) is located in bore (12-1) and male rotor (16) is located in bore (12-2). A wear resistant coating is deposited on the tips (14-1, 16-1) of the rotors. A conformable coating is deposited on the valleys (14-2, 16-2) of the rotors. A conformable coating is depsoited on the surface of the bores coacting with the rotors.