Abstract: Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.

Abstract: A dual-mode mobile terminal, which can access synchronous and asynchronous mobile communication systems, includes a key input panel and a controller. The key input panel includes a call switching key for switching between calls from the two systems and a call end key for ending calls from the two systems. While the terminal performs communication of one call received from one of the two systems in a general communication mode over a communication channel currently established by the one system, the controller determines whether an incoming call is received from the other system. If the incoming call is received, the controller notifies the user of receipt of the incoming call. If the call switching key is pressed, the controller prepares a communication environment for communication of the incoming call, allowing the user to perform the communication of the incoming call while maintaining the currently established communication channel.

Abstract: Phosphate biosensors are disclosed, which comprise a phosphate binding domain conjugated to donor and fluorescent moieties that permit detection and measurement of Fluorescence Resonance Energy Transfer upon phosphate binding. Such biosensors are useful for real time monitoring of phosphate metabolism in living cells.

Abstract: A method for fabricating a semiconductor device includes forming a first insulating layer over a substrate where a landing contact plug is formed, forming an etch barrier pattern having a line type open region over the first insulating layer, forming a second insulating layer for planarization over the etch barrier pattern, forming a contact mask having a hole type open region over the second insulating layer, performing a self-aligned contact etching process using the etch barrier pattern to etch the second insulating layer disposed under the hole type open region and the first insulating layer disposed under the line type open region to form a contact hole a bottom of which is opened above the landing contact plug, forming a storage node contact plug in the contact hole, and forming a storage node over the storage node contact plug.

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased.

Abstract: A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench.

Abstract: Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

Abstract: The present invention relates to a microchip using polyelectrolyte salt bridge for cytometry, velocimetry, and cell sorting. The microchip comprises; a) an inlet for solution to be analyzed, b) a microchannel which provides a moving passage for solution to be analyzed, c) at least one outlet for solution to be analyzed which has passed through the moving passage, d) at least one electrode system comprising a first and a second salt bridges connected to the microchannel (the two salt bridges face each other), and a first and a second reservoirs connected to said each salt bridge (the reservoir comprises electrode and standard electrolyte solution). The microchip detects analytes in the solution to be analyzed (for example, a cell) by detecting change of impedance. In detail, anion in the standard electrolyte solution, which is comprised in the first reservoir, moves from the first salt bridge to the second salt bridge across the microchannel.

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased.

Abstract: A method for fabricating a micropattern of a semiconductor device is provided. The method includes forming a first hard mask over an etch target layer, forming a first sacrificial layer over the first hard mask, etching the first sacrificial layer to form a sacrificial pattern and forming spacers on both sidewalls of the sacrificial pattern, A second sacrificial layer is formed over the spacers and the first hard mask. A dummy mask is formed in a bent portion of the second sacrificial layer between the adjacent spacers. The sacrificial pattern and the second sacrificial layer are etched using the dummy mask and the spacers as an etch barrier layer to form a dummy pattern between the adjacent spacers. The first hard mask is etched using the spacers and the dummy pattern as an etch barrier layer to form a first hard mask pattern.

Abstract: A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars.

Abstract: The present invention generally relates to processes for preparing highly pure morphinan-6-one products. The processes involve reducing the concentration of ?,?-unsaturated ketone compounds present as impurities in morphinan 6 one products or reaction mixtures including morphinan 6 one compounds by treatment with a sulfur-containing compound.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract: A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on sidewalls of the first contact hole, forming a second contact hole to expose the substrate by etching the remaining insulation layer within the first contact hole, forming a third contact hole by horizontally etching the second contact hole, wherein a line width of the third contact hole is wider than that of the first contact hole, and removing the hard mask pattern and the spacer.

Abstract: Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.

Abstract: Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT).

Abstract: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Abstract: A lead frame and a method of manufacturing said lead frame is provided wherein a base material with first and second planar sides is first selectively etched from the first side thereof to a predetermined etching level to create etched areas. The etched areas on the first side of the said base material are then filled with a filling compound and thereafter, the base material is etched from the second side to the etching level to expose the filling compound on the second side.

Abstract: Compounds of formula (I) wherein R1, R3, R4, R5, R6, R7, and R10 are as defined in the specification, are described. The present invention also relates to pharmaceutical composition comprising said compounds and to the use of said compounds in therapy. The present invention further relates to processes for the preparation of said compounds and to new intermediates useful in the preparation thereof. Beside, the invention relates to salts and polymorphic forms of the new compounds as well as the preparation thereof.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.