Abstract: A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.

Abstract: Disclosed are a USB peripheral apparatus capable of reducing transmission power of a transmission terminal circuit by significantly increasing resistance values of terminations provided at the transmission terminal circuit and a reception terminal circuit as compared with a specific impedance value of a transmission line, and a transmission power reduction method thereof.

Abstract: A delayed locked loop (DLL) adjusts a duty cycle of an input clock signal and outputs an output clock signal. The DLL includes a phase and duty cycle detector configured to detect a phase and duty cycle of the input clock signal, a duty cycle corrector configured to correct the duty cycle, a control code generator configured to detect coarse lock of the DLL and generate a binary control code corresponding to the detection result, and a delay circuit configured to delay an output signal of the duty cycle corrector by a predetermined time according to the binary control code, tune the duty cycle thereof, and mix the phase thereof, wherein the phase and duty cycle detector, the duty cycle corrector, the control code generator, and the delay circuit form a feedback loop.

Abstract: The present invention relates to a low-power and high-speed transmission and reception apparatus which reduces consumption power of a sending-end circuit by increasing a value of a termination resistor included in a sending-end circuit and a receiving-end circuit so that the value is greater than a characteristic impedance value of a transmission line.

Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.

Abstract: A delayed locked loop (DLL) adjusts a duty cycle of an input clock signal and outputs an output clock signal. The DLL includes a phase and duty cycle detector configured to detect a phase and duty cycle of the input clock signal, a duty cycle corrector configured to correct the duty cycle, a control code generator configured to detect coarse lock of the DLL and generate a binary control code corresponding to the detection result, and a delay circuit configured to delay an output signal of the duty cycle corrector by a predetermined time according to the binary control code, tune the duty cycle thereof, and mix the phase thereof, wherein the phase and duty cycle detector, the duty cycle corrector, the control code generator, and the delay circuit form a feedback loop.

Abstract: A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.

Abstract: A transmitter system for transmitting parallel data by compensating a crosstalk includes: first and second transmission lines parallel to each other; a first inverted crosstalk pulse generation unit configured to receive first transmission data and inverted first transmission data and output a first inverted crosstalk pulse according to a data mode; a second inverted crosstalk pulse generation unit configured to receive second transmission data transmitted in parallel to the first transmission data and inverted second transmission data and output a second inverted crosstalk pulse according to the data mode; a first addition unit configured to combine the first transmission data and the second inverted crosstalk pulse and output first compensation data to be transmitted to the first transmission line; and a second addition unit configured to combine the second transmission data and the first inverted crosstalk pulse and output second compensation data to be transmitted to the second transmission line.

Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.

Abstract: A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode.

Abstract: An analog beamformer of an ultrasonic diagnosis apparatus includes: a plurality of unit analog beamformers allocated to two or more focal points, respectively, and configured to beamform signals received from the respective focal points through transducer elements and output the beamformed signals; an analog multiplexer configured to sequentially select the output signals of the unit analog beamformers and generate a final output signal; a clock generator configured to provide a clock signal required for the unit analog beamformers; and a processor configured to provide information on sampling time points of channels, and sequentially operate the unit analog beamformers to perform beamforming according to a time-interleaving scheme.

Abstract: A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.

Abstract: A micro-strip transmission line capable of reducing far-end crosstalk is provided. The micro-strip transmission line having a serpentine shape is capable of reducing the far-end crosstalk of the transmission line by increasing capacitive coupling between neighboring transmission lines by allowing parallel micro-strip transmission lines to have serpentine shapes. In the structure of the micro-strip transmission line having the serpentine shape, it is possible to reduce the far-end crosstalk of the transmission line by increasing capacitive coupling between neighboring transmission lines by allowing parallel micro-strip transmission lines to have serpentine shapes.

Abstract: A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode.

Abstract: The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.

Abstract: Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a capacitive coupling between adjacent signal lines is smaller than an inductive coupling therebetween, so that far-end crosstalk occurs. According to the present invention, the capacitive coupling between the adjacent signal lines is increased to reduce the far-end crosstalk. A vertical-stub type microstrip transmission line is provided.

Abstract: A transmitter circuit for transmitting parallel data, suitable for compensating for influence of crosstalk noise in a pre-emphasis scheme. The transmitter circuit includes first through Nth transmission lines configured to respectively transmit first through Nth data (N is 2 or greater); first through Nth output driving circuit sections configured to output the first through Nth data transmitted through the first through Nth transmission lines; first through Nth pre-emphasis circuit sections configured to generate first through Nth pre-emphasis signals for controlling transition output levels of the first through Nth data depending upon signal modes of adjoining data among the first through Nth data; and first through Nth adders configured to generate first through Nth data output signals that are controlled in transition output levels using output signals of the first through Nth output driving circuit sections and the first through Nth pre-emphasis signals.

Abstract: A transmitter system for transmitting parallel data by compensating a crosstalk includes: first and second transmission lines parallel to each other; a first inverted crosstalk pulse generation unit configured to receive first transmission data and inverted first transmission data and output a first inverted crosstalk pulse according to a data mode; a second inverted crosstalk pulse generation unit configured to receive second transmission data transmitted in parallel to the first transmission data and inverted second transmission data and output a second inverted crosstalk pulse according to the data mode; a first addition unit configured to combine the first transmission data and the second inverted crosstalk pulse and output first compensation data to be transmitted to the first transmission line; and a second addition unit configured to combine the second transmission data and the first inverted crosstalk pulse and output second compensation data to be transmitted to the second transmission line.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.

Abstract: Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a capacitive coupling between adjacent signal lines is smaller than an inductive coupling therebetween, so that far-end crosstalk occurs. According to the present invention, the capacitive coupling between the adjacent signal lines is increased to reduce the far-end crosstalk. A vertical-stub type microstrip transmission line is provided.