Abstract: Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value.

Abstract: Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used.

Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.

Abstract: A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second input signal, to provide a first and a second equalized external data signal; a clock synthesizer for outputting sampling clocks, a timing thereof being adjusted by receiving an external clock synchronized with the external data signal; an over-sampler for over-sampling the first and the second equalized external data signal in synchronization with the sampling clocks. A MUX block for multiplexing the outputs of the over-sampler in response to outputs of the MUX block, to thereby attain decision results; and a phase detector for deciding the timing of the sampling clock by analyzing the decision results.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Abstract: Provided is a dual loop DLL for generating an internal clock signal synchronized with an external clock, which includes a reference DLL receiving a reference clock and generating a plurality of phase clock signals having a first phase difference, a coarse loop selecting one of the phase clock signals and generating first through third digital codes to allow the internal clock signal to have a phase difference smaller than a second phase difference with respect to the external clock, and a fine loop selecting two of the phase clock signals and synchronizing the internal clock signal with the external clock, in response to the first through third digital codes.

Abstract: Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.

Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.

Abstract: A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k digit data D (=Dm/k−1Dm/k−2 . . . Di . . . DiDo). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.

Abstract: A receiver performs on data to clock skew compensation by compensating ISI between signals, the ISI being caused by a bandwidth limitation generated in case of chip-to-chip communications in a digital system. A problem of an attenuation of a high frequency signal may occur due to an attenuation in a channel in case of a transmission of a signal at a high speed in the digital system. Therefore there is a limitation in transmitting data at a high speed. The receiver provides a circuit for applying an equalizing technology at the terminal of the receiver. And by compensating for the attenuation of a high frequency component of the signal by using the circuit, the transmission of a signal at a high speed is realized by over-sampling the signal and compensating the data to clock skew.

Abstract: Provided is an adaptive loop bandwidth phase locked loop (PLL) including a deglitch circuit for providing short lock time. The adaptive loop bandwidth can perform a lock operation without having any bad influence on other devices and can detect a difference between the frequency and phase of a signal using a deglitch circuit in an adaptive loop bandwidth manner that can provide short lock time.

Abstract: A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a predetermined first input signal and a predetermined second input signal, to provide a first equalized external data signal and a second equalized external data signal, respectively; a clock synthesizer for outputting a plurality of sampling clocks, a timing thereof being adjusted by receiving an external clock synchronized with the external data signal; an over-sampler for over-sampling the first equalized external data signal and the second equalized external data signal in synchronization with the sampling clocks; a MUX block for multiplexing the outputs of the over-sampler in response to preceding outputs of the MUX block, which are fed back thereto, to thereby attain MUX decision results; and a phase detector for deciding the timing of the sampling clock by analyzing the MUX decision results.

Abstract: A receiver performs on data to clock skew compensation by compensating ISI between signals, the ISI being caused by a bandwidth limitation generated in case of chip-to-chip communications in a digital system. A problem of an attenuation of a high frequency signal may occur due to an attenuation in a channel in case of a transmission of a signal at a high speed in the digital system. Therefore there is a limitation in transmitting data at a high speed. The receiver provides a circuit for applying an equalizing technology at the terminal of the receiver. And by compensating for the attenuation of a high frequency component of the signal by using the circuit, the transmission of a signal at a high speed is realized by over-sampling the signal and compensating the data to clock skew.

Abstract: A programmable high speed frequency divider, in which flip-flops for forming a frequency divider which is capable of being programmed with a programmable dividing ratio is simplified increase the speed of the frequency divider. By simplifying the least significant bit flip-flops, including the flip-flop representing the least significant bit, among flip-flops forming a frequency divider, the speed of the counter in the frequency divider is increased and the frequency limit of an input clock which can be divided is raised.

Abstract: A digital multiplication apparatus and method adopting a redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k-digit data D(=Dm,k−1Dm/k−2 . . . Di . . . DiD0). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.

Abstract: A programmable high speed frequency divider, in which the construction of flip-flops for forming a frequency divider which is capable of programming the dividing ratio of an input clock frequency is simplified in order to increase the operation speed of the frequency divider, is provided. By simplifying the structures of least significant bit flip-flops, including the flip-flop representing the least significant bit, among flip-flops forming a frequency divider, the operation speed of the counter in the frequency divider is increased and the frequency limit of an input clock which can be divided is raised.

Abstract: A high voltage generator provides a high voltage signal for compensating a threshold voltage loss in a semiconductor memory device. The high voltage generator includes: a level detection unit for detecting a voltage level of the high voltage signal to generate a high voltage enable signal when the voltage level of the high voltage signal reaches a predetermined target value; an oscillation unit, in response to the high voltage enable signal, for generating a plurality of clocks, the clocks including a first to a fourth clocks; a high-voltage charge pump unit, in response to the clocks, for increasing a voltage level of an external power signal to generate the high voltage signal to a high voltage node; and a power-on precharging unit, in response to a control signal, for initializing the high voltage node to a predetermined level.

Abstract: A high voltage generator provides a high voltage signal for compensating a threshold voltage loss in a semiconductor memory device. The high voltage generator includes: a level detection unit for detecting a voltage level of the high voltage signal to generate a high voltage enable signal when the voltage level of the high voltage signal reaches a predetermined target value; an oscillation unit, in response to the high voltage enable signal, for generating a plurality of clocks, the clocks including a first to a fourth clocks; a high-voltage charge pump unit, in response to the clocks, for increasing a voltage level of an external power signal to generate the high voltage signal to a high voltage node; and a power-on precharging unit, in response to a control signal, for initializing the high voltage node to a predetermined level.

Abstract: A current-mode bidirectional input/output buffer circuit for impedance matching and operation at a high speed. The current-mode bidirectional input/output buffer circuit communicates with an external chip having the same current-mode bidirectional input/output buffer. In the buffer, a transmitting-receiving average voltage output unit converts an average current value between a transmission signal to be transmitted to the external chip and a receiving signal transmitted from the external chip, into an average voltage. A reference voltage output unit converts a reference current value selectively generated according to a voltage level of the transmission signal, into a reference voltage. A comparator compares the voltage from the transmitting-receiving average voltage output unit to the voltage from the reference voltage output unit to provide a logic signal corresponding to the received signal transmitted from the external chip.

Abstract: A circuit for selectively generating one of three voltage level as an output has a pull-up transistor and a pull-down transistor. The circuit includes a bias voltage source for generating a constant voltage signal; a temperature compensating constant-current source for outputting variable voltage signal corresponding to a temperature change; a tri-state control circuit for receiving a data signal to generate a control signal based on the data signal; and a switching circuit, in response to the control signal, for selectively the bias voltage source and the temperature compensating constant current source to the pull-up and pull-down transistors.