Abstract: A method of producing a thin film transistor substrate to prevent an interconnection from being corroded during a dry etching process includes sequentially forming on an insulating substrate a gate interconnection, a gate insulating layer, an active layer, a conductive layer for a data interconnection, and a photoresist pattern including a first region and a second region, etching the conductive layer for the data interconnection using the photoresist pattern as an etching mask to form a conductive layer pattern for source/drain electrodes, etching the active layer using the photoresist pattern as the etching mask to form an active layer pattern, removing the second region of the photoresist pattern, dry etching the conductive layer pattern for the source/drain electrodes under the second region using the photoresist pattern as the etching mask and etching gas, etching a portion of the active layer pattern using the photoresist pattern as the etching mask, and physically removing the reaction byproduct using

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: A method for forming a metal line includes sequentially depositing a low-resistivity metal layer having aluminum on a base substrate and an upper layer having molybdenum on the low-resistivity metal layer, forming a photoresist pattern having a linear shape on the upper layer, etching the upper layer via a mixed gas using the photoresist pattern as a mask, the mixed gas including a chlorine based gas mixed with an additional gas having at least one of nitrogen gas, argon gas, helium gas and sulfur hexafluoride gas, and etching the low-resistivity metal layer using the photoresist pattern as the mask thereby removing any stringer that may be caused by a residue of the low-resistivity metal layer.

Abstract: In a method for forming a metal line, a first metal layer and a second metal layer are deposited on a substrate. The first metal layer includes aluminum, and the second metal layer includes molybdenum. A photoresist pattern having a line-shape is formed on the second metal layer. The second metal layer is etched with a chlorine-containing etching gas using the photoresist pattern as a mask. The first metal layer is then etched with a mixture of a chlorine-containing gas and nitrogen gas and/or a mixture of a chlorine-containing gas and argon gas as an etching gas. Impurities such as chlorine ions are removed from the base substrate after etching the first metal layer with a fluorine-containing gas, hydrogen gas, or water vapor. A method for manufacturing a display substrate is disclosed using the method for forming a metal line to form source, drain, and gate electrodes and gate lines.

Abstract: A display substrate includes a gate line, a storage capacitor, a source line, a switching element, a pixel electrode, and a color filter. The gate line is formed on a base substrate. The storage capacitor has a storage line substantially parallel to the gate line. The source line crosses the gate line to define a pixel area. The switching element is connected to the gate line and the source line. The pixel electrode contacts the switching element. The color filter pattern is formed between the base substrate and the pixel electrode such that the color filter pattern contracts the base substrate and the pixel electrode. Thus, the color filter pattern is formed on the display substrate using a three-mask process.

Abstract: A thin film transistor (TFT) array substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion, and a method of fabricating the TFT array substrate. The TFT array substrate includes a gate interconnection line arranged on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode, and a drain electrode arranged on the semiconductor layer, a first passivation film arranged on the data interconnection line and exposing the drain electrode, a second passivation film arranged on the first passivation film, and a pixel electrode electrically connected with the drain electrode. An outer sidewall of the second passivation film is positioned inside an outer sidewall of the first passivation film.

Abstract: A display apparatus includes a first substrate, a gate line formed on the first substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line formed on the semiconductor layer and including a source electrode, a drain electrode facing the source electrode, a first electrode electrically connected to the drain electrode, in a second substrate facing the first substrate, a second electrode formed on the second substrate, and a liquid crystal layer disposed between the first electrode and the second electrode. At least one of the first and second electrodes includes a plurality of line patterns to polarize incident light.

Abstract: A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.

Abstract: A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.

Abstract: A method of manufacturing a display substrate includes forming a first metallic pattern including gate and storage conductors and a gate electrode of a switching device on a base substrate, forming a gate insulation layer, forming a second metallic pattern and a channel portion including a source line, source and drain electrodes of the switching device, forming a passivation layer and a photoresist film on the second metallic pattern, patterning the photoresist film to form a first pattern portion corresponding to the gate and source conductors and the switching device, and a second pattern portion formed on the storage line, etching the passivation layer and the gate insulation layer, and forming a pixel electrode using the first pattern portion. Therefore, excessive etching of the stepped portion may be prevented, so that a short-circuit defect between a metallic pattern and a pixel electrode may be prevented.

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: In one embodiment, a thin film transistor array display panel and method of manufacturing the same are provided. A method includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; forming a data layer on the ohmic contact layer; forming a photosensitive pattern on the data layer; etching the data layer to form a data line including a source electrode and a drain electrode that is opposite to the source electrode; reflowing the photosensitive pattern to cover side surfaces of the source electrode and the drain electrode; and etching the ohmic contact layer using the reflowed photosensitive pattern as a mask.

Abstract: A flexible display panel according to an embodiment of the present invention includes a flexible substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the substrate, a semiconductor layer formed on the gate insulating layer and disposed substantially on the entire gate electrode, a source electrode and a drain electrode formed on the semiconductor layer, and a pixel electrode connected to the drain electrode. The patterning of the semiconductor layer to form a second semiconductor member may include coating a photoresist film on a first semiconductor member, exposing the photoresist film to light from a back of the substrate, wherein the gate electrode is used as a light blocking mask, developing the exposed photoresist film to form a photoresist pattern having the same planar size as the gate electrode, and etching the semiconductor layer using the photoresist pattern as an etching mask.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract: A method for forming a contact hole includes forming a conductive layer on a substrate, patterning the conductive layer to form a wiring, forming an insulating layer on the wiring and the substrate through a low temperature process, and dry etching the insulating layer using an anoxic gas to expose the wiring.

Abstract: Provided are a thin film transistor (TFT) substrate and a method for manufacturing the same. The method comprises forming on a substrate a conductive layer, an impurity-doped silicon layer, and an intermediate layer, wherein the intermediate layer comprises intrinsic silicon; patterning the intermediate layer, the impurity-doped silicon layer, and the conductive layer to form a data line, a source electrode, a drain electrode, ohmic contact portions, and intermediate portions, wherein an ohmic contact portion and an intermediate portion are on the source electrode, and an ohmic contact portion and an intermediate portion are on the drain electrode; forming an intrinsic silicon layer on the substrate; and patterning the intrinsic silicon layer to form a semiconductor layer forming channel portion between the source electrode and the drain electrode, and a contact portion on the intermediate portion.

Abstract: A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

Abstract: The present invention relates to a plasma apparatus comprising a reaction chamber having a reaction space which accommodates a substrate to be treated; a coil located on the outside of the reaction space; a power source applying alternating frequency power on the coil; and a conducting plate located between the coil and the reaction space and generating an induced current from the alternating frequency power applied on the coil. Thus, the present invention provides a plasma apparatus that induces a uniform electric field in an internal gas of the reaction chamber.

Abstract: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

Abstract: A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.