Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.

Abstract: An approach is provided in which an information handling system creates a set of first containers from a container image that each includes a set of shareable files. The information handling system creates a second container from the container image that is devoid of the set of shared files and includes a pointer that points to a selected one of the first containers. In turn, the second container mounts to the first container and utilizes the shared files included the first container.

Abstract: An approach is provided in which an information handling system creates a set of first containers from a container image that each includes a set of shareable files. The information handling system creates a second container from the container image that is devoid of the set of shared files and includes a pointer that points to a selected one of the first containers. In turn, the second container mounts to the first container and utilizes the shared files included the first container.

Abstract: The embodiment of the present disclosure provides an antenna structure and an antenna array. The antenna structure comprises a first antenna component which comprises: a first three-dimensional antenna with one end grounded or connected with a reference potential; a single antenna port connected with the other end of the first three-dimensional antenna; and a first parasitic structure provided adjacent to the first three-dimensional antenna. In the antenna structure, the first three-dimensional antenna is only connected with a single antenna port, so that the number of ports required by the antenna can be reduced, that is, the power consumption can be reduced from the antenna dimension, thereby simultaneously reducing heat generation and maintaining stable overall wireless performance.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: The present invention relates to an integration module system of millimeter-wave and non-millimeter-wave antennas and an electronic apparatus, the system comprising a millimeter-wave antenna module and a non-millimeter-wave environment, the millimeter-wave antenna module forming a communication connection with the non-millimeter-wave environment for realizing reusing of the millimeter-wave antenna module to achieve a function of non-millimeter-wave antenna(s). The present invention proposes directly reusing a millimeter-wave antenna module, which is designed so that this module also has an antenna function of a non-millimeter-wave module, while an individual module's own volume does not need to be increased, and the module itself does not need to have additionally-added antenna traces, that is, with the same volume, a function of non-millimeter-wave antenna(s) may be further added.

Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.

Abstract: A user equipment (UE) and a Secure User Plane Location (SUPL) Location Platform (SLP) support a SUPL positioning session for at least one uplink or uplink-downlink position method, such as uplink Angle of Arrival or multi-Round Trip Time. To support SUPL positioning for uplink or uplink-downlink position methods, the UE provides an identifier for a serving Access and Mobility Management Function (AMF) and an identifier for the UE to the SLP in a SUPL message. The SLP may exchange positioning messages with a serving base station for the UE using the identifier for the serving AMF and the identifier for the UE. The exchange of positioning messages may enable the SLP to request the serving base station to instigate transmission of uplink positioning reference signals by the UE which may be a key enabler for an uplink or uplink-downlink position method.

Abstract: The present application provides a method for producing recombinant adenovirus. The method comprises expansion of the recombinant adenovirus packaging cells from the Working Cell Bank and re-expansion of the cells after inoculation in a packed bed bioreactor in order to obtain a re-expanded recombinant adenovirus. The present application also provides the use of a packed bed bioreactor for recombinant adenovirus production.

Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.

Abstract: A storage module of distributed flow battery is provided. An electrochemical reaction is processed with the positive and negative electrolytes to produce and/or discharge direct current and further output the positive and negative electrolytes after the reaction. The module comprises two end plates; two frames disposed between the two end plates; two current collectors disposed between the two frames; two complex cast polar plates disposed between the two current collectors; two electrodes disposed between the two complex cast polar plates; a membrane disposed between the two electrodes; and three gaskets. Therein, two of the gaskets are set to sandwich and enclose one of the two complex cast polar plates; and the other one of the gaskets is set between the other one of the two complex cast polar plates and an adjacent one of the current collectors.

Abstract: A data driving circuit proofed against excessive pixel brightness because of overvoltage on the data line comprises a shift register circuit, a first latch circuit, a second latch circuit, a level shift circuit, a DAC circuit, and an output circuit. The second latch circuit detects a change in the MSB of the data signal of a sampled signal, and outputs a signal for applying a pre-operation of the current data line. When the MSB of the sampled signal is changed, the second latch circuit outputs a pre-operation enabling signal, and whether the grayscale value of the current data line is within a specified region. If within the specified region, the second latch circuit outputs an invalid signal, and the pre-operation is disabled.

Abstract: The disclosure is directed to compounds of Formula I Pharmaceutical compositions comprising compounds of Formula I, as well as methods of their use and preparation, are also described.

Abstract: An automatic powering device includes a dielectric layer, a driving layer, a plurality of electrodes and a droplet. The dielectric layer includes a first surface and a second surface opposite to the first surface. The driving layer faces toward the dielectric layer thereby forming a channel between the driving layer and the dielectric layer. The driving layer includes a plurality of hydrophilic surfaces facing toward the first surface and a plurality of hydrophobic surfaces facing toward the first surface. Each of the hydrophilic surfaces is staggered from each of the hydrophobic surfaces. The electrodes are disposed at the second surfaces. The electrodes each are electrically connected to and spaced from each other. The droplet is flowable within the channel. The droplet is affected by the hydrophilic surfaces and the hydrophobic surfaces so as to flow in the channel.

Abstract: A triboelectric nanogenerator structure is provided. The triboelectric nanogenerator structure is composed of an upper electrode layer, a lower triboelectric layer, a lower electrode layer and an electric connecting member. The upper electrode layer is composed of a hybrid gel. The lower triboelectric layer corresponding to the upper electrode layer has a first surface and a second surface, and the first surface faces toward the upper electrode layer. The lower electrode layer is disposed at the second surface. The electric connecting member connects the upper electrode layer to the lower electrode layer.

Abstract: The present invention relates to a diverse integration module system of millimeter-wave and non-millimeter-wave antennas and an electronic apparatus, the diverse integration module system of antennas comprising an integration module of millimeter-wave and non-millimeter-wave antennas and a non-millimeter-wave environment, the integration module of millimeter-wave and non-millimeter-wave antennas comprising a millimeter-wave antenna module provided with one or more first non-millimeter-wave antennas, the millimeter-wave antenna module being further provided thereon with a first communication part that is communicatively connected to the non-millimeter-wave environment, both the first non-millimeter-wave antenna(s) and the first communication part forming a communication connection with the non-millimeter-wave environment and a method for designing non-millimeter-wave antenna(s) on a millimeter-wave antenna module and simultaneously further directly reusing the millimeter-wave antenna module.