Abstract: Systems, methods, and apparatuses are disclosed herein for aggregating packets and transmitting the aggregated packets to a device in an integrated circuit. These systems, methods, and apparatuses may include receiving, at a buffer of a System-on-Chip (“SoC”), a plurality of packets for output. The SoC may determine, when each packet of the plurality of output packets is received, whether the buffer has reached a predetermined capacity. In response to determining that the buffer has reached the predetermined capacity, the SoC may identify a subset of packets of the plurality of packets that share a common characteristic, may aggregate the subset into a jumbo packet, and may transmit the jumbo packet to a destination SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for identifying a topology of a MoChi system prior to a boot-up of an operating system. A master SoC may detect, prior to boot-up of an operating system that uses the master SoC, an initialization command, and may, in response to detecting the initialization command, assign a first chip identifier to the master SoC. The master SoC may transmit a discovery communication from the master SoC to a slave SoC that is one hop away from the master SoC. The slave SoC may determine whether the slave SoC is a last hop SoC, and, in response to determining that the slave SoC is a last hop SoC, the slave SoC may transmit a reply communication to the master SoC. The master SoC may then assign, based on the reply communication, a second chip identifier to the slave SoC.

Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.

Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.

Abstract: A system-on-chip including non-hopping bus interfaces and a hopping bus. The non-hopping bus interfaces include a first non-hopping bus interface and a second non-hopping bus interface. The first non-hopping bus interface is configured to, based on a first protocol, receive information. The hopping bus includes intra-chip adaptors. The intra-chip adaptors are connected in series and respectively to the non-hopping bus interfaces. The intra-chip adaptors are configured to (i) according to a second protocol, convert the information into a first format for transmission over the hopping bus, and (ii) transfer the information in the first format over the hopping bus and between the intra-chip adaptors. The second protocol is different than the first protocol. The second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus.

Abstract: A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network.

Abstract: Systems, methods, and apparatuses are disclosed herein for identifying a topology of a MoChi system prior to a boot-up of an operating system. A master SoC may detect, prior to boot-up of an operating system that uses the master SoC, an initialization command, and may, in response to detecting the initialization command, assign a first chip identifier to the master SoC. The master SoC may transmit a discovery communication from the master SoC to a slave SoC that is one hop away from the master SoC. The slave SoC may determine whether the slave SoC is a last hop SoC, and, in response to determining that the slave SoC is a last hop SoC, the slave SoC may transmit a reply communication to the master SoC. The master SoC may then assign, based on the reply communication, a second chip identifier to the slave SoC.

Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.

Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.

Abstract: Systems, methods, and apparatuses are disclosed herein for aggregating packets and transmitting the aggregated packets to a device in an integrated circuit. These systems, methods, and apparatuses may include receiving, at a buffer of a System-on-Chip (“SoC”), a plurality of packets for output. The SoC may determine, when each packet of the plurality of output packets is received, whether the buffer has reached a predetermined capacity. In response to determining that the buffer has reached the predetermined capacity, the SoC may identify a subset of packets of the plurality of packets that share a common characteristic, may aggregate the subset into a jumbo packet, and may transmit the jumbo packet to a destination SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.

Abstract: A system including a first system-on-chip (SoC) and a second SoC. The first SoC includes a first module and a second module. The second module is separate from the first module. The second module is in communication with the first module via a first bus. The first bus is internal to the first SoC. The second SoC is separate from the first SoC. The second SoC is in communication with the first SoC via a second bus. The second bus is external to both the first SoC and the second SoC. The first bus and the second bus are configured to use a same communication protocol to respectively transfer information (i) between the first module and the second module via the first bus and internally within the first SoC and (ii) between the first SoC and the second SoC via the second bus.

Abstract: A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network.

Abstract: A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network.

Abstract: Techniques for a precoding scheme for wireless communications are described. A method and apparatus may comprise a first device for a communications system to determine a beamforming structure for a closed loop transmit beamforming scheme using channel information, one or more scaling factors and one or more integers to represent a complex vector. The beamforming structure may include a codeword, a codebook and a codeword index. Other embodiments are described and claimed.

Abstract: A system including a first system-on-chip (SoC) and a second SoC. The first SoC includes a first module and a second module. The second module is separate from the first module. The second module is in communication with the first module via a first bus. The first bus is internal to the first SoC. The second SoC is separate from the first SoC. The second SoC is in communication with the first SoC via a second bus. The second bus is external to both the first SoC and the second SoC. The first bus and the second bus are configured to use a same communication protocol to respectively transfer information (i) between the first module and the second module via the first bus and internally within the first SoC and (ii) between the first SoC and the second SoC via the second bus.

Abstract: An embodiment of the present invention provides a method, comprising using an adaptive codebook for beamforming for communications in wireless networks.

Abstract: A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network.

Abstract: A system-on-chip including non-hopping bus interfaces and a hopping bus. The non-hopping bus interfaces include a first non-hopping bus interface and a second non-hopping bus interface. The first non-hopping bus interface is configured to, based on a first protocol, receive information. The hopping bus includes intra-chip adaptors. The intra-chip adaptors are connected in series and respectively to the non-hopping bus interfaces. The intra-chip adaptors are configured to (i) according to a second protocol, convert the information into a first format for transmission over the hopping bus, and (ii) transfer the information in the first format over the hopping bus and between the intra-chip adaptors. The second protocol is different than the first protocol. The second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus.