Patents by Inventor Hong Rak Son

Hong Rak Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12019871
    Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: June 25, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngsuk Ra, Hanbyeul Na, Kwanwoo Noh, Mankeun Seo, Hong Rak Son, Jae Hun Jang
  • Publication number: 20240128986
    Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.
    Type: Application
    Filed: May 17, 2023
    Publication date: April 18, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: YongSung KIL, Soonyoung Kang, Hong Rak Son, Kangseok Lee
  • Publication number: 20240106462
    Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.
    Type: Application
    Filed: April 28, 2023
    Publication date: March 28, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Yeol Yang, BOHWAN JUN, HONG RAK SON, GEUNYEONG YU, YOUNGJUN HWANG
  • Publication number: 20240079073
    Abstract: Disclosed is a method of operating a storage controller which is configured to communicate with a non-volatile memory device. The method includes receiving count data from the non-volatile memory device, determining a pre-read voltage based on the count data, sending a pre-read request using the pre-read voltage to the non-volatile memory device, receiving pre-read data from the non-volatile memory device responsive to sending the pre-read request, calculating a decoding value corresponding to the pre-read data, and generating read voltage information based on the count data and the decoding value, and the decoding value predicts an error voltage of the pre-read data.
    Type: Application
    Filed: May 19, 2023
    Publication date: March 7, 2024
    Inventors: YongSung Kil, Soonyoung Kang, Hong Rak Son, Kangseok Lee
  • Publication number: 20240072992
    Abstract: A homomorphic encryption operator includes: a level configuration unit configured to set an encryption level by selecting a plurality of prime numbers of different values according to a scale factor condition used for multiplication of a homomorphic encryption operation and an increase/decrease condition for increasing or decreasing consecutively selected prime numbers, and a modular multiplication operator configured to perform lightweight modular multiplication using the selected plurality of prime numbers, wherein the level configuration unit includes: a level constructor configured to select prime number sets whose number have selected Hamming weights, respectively, based on the scale factor condition and the increase/decrease condition, and wherein the level configuration unit is further configured to configure the selected prime number sets with the encryption level using a prime number table.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Inventors: YOUNG SIK MOON, JIYOUP KIM, HANBYEUL NA, HONG RAK SON, SEONGHYEOG CHOI
  • Patent number: 11836606
    Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Soo Lim, Chang Kyu Seol, Jae Hun Jang, Hye Jeong So, Hong Rak Son, Pil Sang Yoon
  • Patent number: 11791846
    Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hun Jang, Dong-Min Shin, Heon Hwa Cheong, Jun Jin Kong, Hong Rak Son, Se Jin Lim
  • Publication number: 20230266916
    Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Inventors: Wi Jik LEE, Dong-Min SHIN, Young Jun HWANG, Hong Rak SON
  • Publication number: 20230185452
    Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.
    Type: Application
    Filed: July 15, 2022
    Publication date: June 15, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngsuk RA, Hanbyeul NA, Kwanwoo NOH, Mankeun SEO, Hong Rak SON, Jae Hun JANG
  • Patent number: 11675530
    Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wi Jik Lee, Dong-Min Shin, Young Jun Hwang, Hong Rak Son
  • Patent number: 11669395
    Abstract: A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: June 6, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Hong-Rak Son
  • Publication number: 20230092380
    Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.
    Type: Application
    Filed: August 11, 2022
    Publication date: March 23, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog CHOI, Dong-Min SHIN, Hong Rak SON, Hyeonjong SONG, Yeongcheol JO
  • Publication number: 20230068302
    Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.
    Type: Application
    Filed: March 18, 2022
    Publication date: March 2, 2023
    Inventors: JAE HUN JANG, JI YOUP KIM, HAN BYEUL NA, YOUNG SUK RA, MAN KEUN SEO, HONG RAK SON, SE JIN LIM
  • Patent number: 11531588
    Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: December 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangseok Lee, Dong-min Shin, Geunyeong Yu, Bohwan Jun, Hee Youl Kwak, Hong Rak Son
  • Patent number: 11526287
    Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyejeong So, Changkyu Seol, Hong Rak Son, Pilsang Yoon, Jinsoo Lim, Jae Hun Jang, Seonghyeong Choi
  • Patent number: 11361832
    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunseung Han, Seonghyeog Choi, Youngsuk Ra, Hong Rak Son, Taehyun Song, Bohwan Jun
  • Publication number: 20220083259
    Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.
    Type: Application
    Filed: April 22, 2021
    Publication date: March 17, 2022
    Inventors: Wi Jik LEE, Dong-Min SHIN, Young Jun HWANG, Hong Rak SON
  • Publication number: 20220035703
    Abstract: A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 3, 2022
    Inventors: DONG-MIN SHIN, HONG-RAK SON
  • Publication number: 20220004458
    Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kangseok LEE, Dong-min SHIN, Geunyeong YU, Bohwan JUN, Hee Youl KWAK, Hong Rak SON
  • Patent number: 11216338
    Abstract: A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjun Hwang, Dong-Min Shin, Changkyu Seol, Jaeyong Son, Hong Rak Son