Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: An apparatus may include a vessel adapted to contain an organic solvent and a dehydration apparatus coupled with the vessel. The dehydration apparatus may be adapted to remove water from the organic solvent. The apparatus may further include a water content monitor coupled to the dehydration apparatus and the vessel, in which the water content monitor is adapted to determine a water content of the organic solvent. The apparatus may further include a wafer handler adapted to transfer at least one semiconductor wafer including a MEMS device into the vessel.

Abstract: Methods and apparatus for MEMS release are disclosed. A method is described including providing a substrate including at least one MEMS device supported by a sacrificial layer; performing an etch in solution to remove the sacrificial layer from at least one MEMS device; immersing the substrate including the at least one MEMS device in an organic solvent; and while the substrate is immersed in the organic solvent, removing water from the organic solvent until the water remaining in the organic solvent is less than a predetermined threshold. An apparatus is disclosed for performing the methods. Additional alternative methods are disclosed.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: Embodiments of mechanisms of an optical inspection system for inspecting an object are provided. The optical inspection system includes a light source emitting a coherent beam having a first width, and a beam expander increasing the first width to a second width. The optical inspection system also includes an polaroid module adjacent to the beam expander and polarizing the coherent beam. The object generates an inspection beam with an interference pattern by reflecting the polarized coherent beam. The optical inspection system further includes an image module capturing the inspection beam.

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.