Patents by Inventor Hong Seon Yang
Hong Seon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038840Abstract: A semiconductor device includes an active pattern with a first impurity having a first conductivity, first and second nanosheets on the active pattern, a gate electrode on the active pattern and surrounding each of the first and second nanosheets, a lower source/drain region on the active pattern, an uppermost surface of the lower source/drain region being lower than a lower surface of the second nanosheet, and the lower source/drain region being doped with a second impurity having the first conductivity, an upper source/drain region on the lower source/drain region, the upper source/drain region being doped with a third impurity having a second conductivity different from the first conductivity, and a gate insulation layer between the gate electrode and the lower and upper source/drain regions, the gate insulation layer being in contact with each of the lower and upper source/drain regions.Type: ApplicationFiled: March 24, 2023Publication date: February 1, 2024Inventors: Dong-Gwan SHIN, Yong Hee PARK, Hong Seon YANG, Hye In CHUNG, Pan Kwi PARK
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Patent number: 10586852Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.Type: GrantFiled: October 10, 2018Date of Patent: March 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Han Lee, Myung Il Kang, Jae Hwan Lee, Sun Wook Kim, Seong Ju Kim, Sung Jin Park, Hong Seon Yang, Joo Hee Jung
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Publication number: 20190051728Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.Type: ApplicationFiled: October 10, 2018Publication date: February 14, 2019Inventors: Jung Han LEE, Myung Il KANG, Jae Hwan LEE, Sun Wook KIM, Seong Ju KIM, Sung Jin PARK, Hong Seon YANG, Joo Hee JUNG
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Patent number: 10109717Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.Type: GrantFiled: May 16, 2017Date of Patent: October 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Han Lee, Myung Il Kang, Jae Hwan Lee, Sun Wook Kim, Seong Ju Kim, Sung Jin Park, Hong Seon Yang, Joo Hee Jung
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Publication number: 20180130890Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.Type: ApplicationFiled: May 16, 2017Publication date: May 10, 2018Inventors: Jung Han LEE, Myung Il KANG, Jae Hwan LEE, Sun Wook KIM, Seong Ju KIM, Sung Jin PARK, Hong Seon YANG, Joo Hee JUNG
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Patent number: 9153446Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.Type: GrantFiled: May 20, 2014Date of Patent: October 6, 2015Assignee: SK Hynix Inc.Inventors: Se-Aug Jang, Hong-Seon Yang, Ja-Chun Ku, Seung-Ryong Lee
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Patent number: 9064854Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.Type: GrantFiled: May 10, 2013Date of Patent: June 23, 2015Assignee: SK hynix Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
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Publication number: 20140256125Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: SK hynix Inc.Inventors: Se-Aug JANG, Hong-Seon YANG, Ja-Chun KU, Seung-Ryong LEE
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Patent number: 8736017Abstract: A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.Type: GrantFiled: June 29, 2009Date of Patent: May 27, 2014Assignee: SK Hynix Inc.Inventors: Se-Aug Jang, Hong-Seon Yang, Ja-Chun Ku, Seung-Ryong Lee
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Patent number: 8592899Abstract: A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.Type: GrantFiled: August 16, 2010Date of Patent: November 26, 2013Assignee: SK hynix Inc.Inventors: Se-Aug Jang, Hong-Seon Yang, Heung-Jae Cho, Min-Gyu Sung, Tae-Yoon Kim, Sook-Joo Kim
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Publication number: 20130241011Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.Type: ApplicationFiled: May 10, 2013Publication date: September 19, 2013Applicant: SK hynix Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
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Patent number: 8441079Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.Type: GrantFiled: March 8, 2011Date of Patent: May 14, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
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Patent number: 8410547Abstract: A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers.Type: GrantFiled: November 30, 2010Date of Patent: April 2, 2013Assignee: Hynix Semiconductor Inc.Inventors: Heung-Jae Cho, Hong-Seon Yang, Se-Aug Jang
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Patent number: 8330215Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.Type: GrantFiled: September 23, 2011Date of Patent: December 11, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
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Patent number: 8319341Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.Type: GrantFiled: August 23, 2010Date of Patent: November 27, 2012Assignee: Hynix Semiconductor Inc.Inventors: Min-Gyu Sung, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim
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Patent number: 8288819Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.Type: GrantFiled: November 23, 2010Date of Patent: October 16, 2012Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Kim, Hong Seon Yang, Se Aug Jang, Seung Ho Pyi, Kwon Hong, Heung Jae Cho, Kwan Yong Lim, Min Gyu Sung, Seung Ryong Lee, Tae Yoon Kim
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Publication number: 20120012928Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
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Patent number: 8048742Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.Type: GrantFiled: June 29, 2007Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
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Patent number: 8008178Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer over a substrate, forming an intermediate structure over the first conductive layer, the intermediate structure formed in a stack structure comprising at least a first metal layer and a nitrogen containing metal silicide layer, and forming a second conductive layer over the intermediate structure.Type: GrantFiled: December 7, 2007Date of Patent: August 30, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung
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Publication number: 20110186920Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.Type: ApplicationFiled: March 8, 2011Publication date: August 4, 2011Applicant: Hynix Semiconductor Inc.Inventors: Kwan-Yong LIM, Hong-Seon Yang, Heung-Jae Cho, Tae-Kyung Kim, Yong-Soo Kim, Min-Gyu Sung