Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.

Abstract: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012° C.-dyne/cm2.

Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

Abstract: The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.

Abstract: Disclosed is a method of manufacturing a semiconductor memory device. An ion implantation layer is formed into a given depth of the semiconductor substrate. Therefore, it is possible to prevent the dopant (P31) gettered on the surface of the semiconductor substrate from being diffused toward the bottom when a well ion is injected. The dopant (P31) gettered on the surface of the semiconductor substrate is easily experienced by transit-enhanced diffusion even at low temperature. Also, the dopant may serve as counter dopping in the buried channel. In the present invention, as the behavior of this dopant (P31) is prohibited in a subsequent annealing process, the concentration of the ion for controlling the threshold voltage could be uniformly kept. Therefore, the present invention can manufacture devices of high reliability having a stable threshold voltage characteristic and can be flexibly applied to manufacturing the devices depending on reduction in the design rule.

Abstract: The present invention discloses a method of manufacturing a TaON capacitor having a high capacity comprising the steps of forming an intermediate insulating layer on a semiconductor substrate; forming a lower electrode on the intermediate insulating layer; depositing a TaON thin film in an amorphous state on the lower electrode; annealing the amorphous TaON thin film in a vacuum state to form a crystalline TaON thin film that will serve as a dielectric layer; and forming an upper electrode on the dielectric layer made of the TaON thin film.

Abstract: The present invention discloses a method of manufacturing a TaON capacitor having a high capacity comprising the steps of forming an intermediate insulating layer on a semiconductor substrate; forming a lower electrode on the intermediate insulating layer; depositing a TaON thin film in an amorphous state on the lower electrode; annealing the amorphous TaON thin film in a vacuum state to form a crystalline TaON thin film that will serve as a dielectric layer; and forming an upper electrode on the dielectric layer made of the TaON thin film.

Abstract: A method for fabricating capacitors for semiconductor devices utilizing a Ta3N5 dielectric layer is provided by the present invention. This method includes the steps of forming a lower electrode on a semiconductor substrate, depositing an amorphous TaON thin film over the lower electrode, and subjecting the deposited amorphous TaON thin film to a thermal process in an NH3 atmosphere, thereby forming a Ta3N5 dielectric film, and forming an upper electrode on the Ta3N5 dielectric film. The resulting Ta3N5 dielectric film provides a dielectric constant significantly greater than those that can be achieved with conventional dielectric films. Accordingly, the Ta3N5 dielectric film of the present invention can be used to manufacture capacitors for the next generation semiconductor memory devices of 256M grade or higher.

Abstract: A method for fabricating capacitors for semiconductor devices utilizing a Ta3N5 dielectric layer is provided by the present invention. This method includes the steps of forming a lower electrode on a semiconductor substrate, depositing an amorphous TaON thin film over the lower electrode, and subjecting the deposited amorphous TaON thin film to a thermal process in an NH3 atmosphere, thereby forming a Ta3N5 dielectric film, and forming an upper electrode on the Ta3N5 dielectric film. The resulting Ta3N5 dielectric film provides a dielectric constant significantly greater than those that can be achieved with conventional dielectric films. Accordingly, the Ta3N5 dielectric film of the present invention can be used to manufacture capacitors for the next generation semiconductor memory devices of 256M grade or higher.

Abstract: The present invention relates to semiconductor manufacturing field, more particularly, to a process of forming a charge storage electrode to which a selective hemispherical grains (HSG) silicon film is applied. The object of the present invention is to provide a method of forming a charge storage electrode having the selective HSG silicon film in semiconductor device which can secure a sufficient capacitor effective surface area by obtaining desired grain size at the time of selective HSG silicon film formation. The present invention prevents remaining of carbon component which obstructs the growth of HSG silicon film after dry etching process by limiting the carbon halide gas used in dry etching process of amorphous silicon film for defining the charge storage electrode at the time of process of forming the charge storage electrode having selective HSG silicon film.

Abstract: The present invention is a method which can obtain an actual value close to a desired capacitance of capacitor by precisely monitoring the area variation rate of film by using a correlation between a height of hemispherical grains formed on a surface of film and a surface area of film. The present invention provides a method of calculating an area variation rate `C.sub.E ` by using the porosity ratio `f.sub.v ` and the height `t` of hemispherical grains and measuring the capacitance of capacitor by using the obtained area variation rate. According to this method, the area variation rate of film can be obtained close to actual value by measuring the height of hemispherical grains formed on the surface of film, and the variation in capacitance before completion of capacitor can be precisely obtained.

Abstract: The present invention relates to a method of manufacturing a polysilicon film having a grain size of 0.5 .mu.m or more by forming a nucleus site of low density at low temperature of about 450.degree. C. with Si.sub.2 H.sub.6 gas, by growing an amorphous silicon film to some degree with the nucleus site, forming an amorphous silicon film of a device to a desired thickness by carrying out a main deposition process at the temperature of 500 through 600.degree. C. with SiH.sub.4 or SiH.sub.4 containing a small amount of impurity, and carrying out a heat treatment process for a long period at the temperature range of 600 through 700.degree. C. with N.sub.2 gas.