Abstract: Rambus Dynamic Random Access Memory (DRAM) devices may have their functional blocks arranged effectively in an integrated circuit substrate. A first memory core block an interface logic block, a pad block, an input/output and internal clock signal generation block, a data shift block and a second memory core block are sequentially arranged in one axial direction of the substrate. Accordingly, the lengths of data lines for transmitting data between a data input/output unit of the input/output and internal clock signal generation block and the data shift block may be reduced so that loads on the data lines may be reduced, thereby allowing data transmission speed to be maintained and/or power consumption to be reduced. Moreover, the data lines need not be wired between pads in the pad block, which can prevent the width of the substrate from increasing.

Abstract: Backbias voltage generation circuit corresponding to the frequency of a chip control signal is disclosed. The circuit includes a normal driving unit, an active driving unit and a level detecting unit. The level detecting unit detects whether a backbias voltage VBB is equal to or higher than a target voltage level. A normal control signal DETN is activated to enable the normal driving unit, and an active control signal DETA is activated to enable the active driving unit. The normal driving unit pumps down the backbias voltage VBB independent of the chip control signal CONC. The active driving unit includes a counter circuit and an active pumping unit. The counter circuit generates first and second edge detecting signals FED and RED in response to an activating edge of the chip control signal CONC. The active pumping unit pumps down the backbias voltage VBB, when the first edge signal FED or second edge signal RED is activated.

Abstract: Integrated circuit memory devices include a sense amplifier which is electrically coupled to a first pair of bit lines (BL and /BL) and is responsive to at least one amplifier enable signal (e.g., AE1, AE2). A preferred driver circuit is also provided. The driver circuit is responsive to a write enable pulse (.phi.WR) and drives the at least one amplifier enable signal to an inactive state (e.g., high impedance state) in response to a leading edge of the write enable pulse and to an active state (Vss or Vcc) in response to a trailing edge of the write enable pulse. The memory device also includes a write enable buffer that generates a write enable pulse in response to a write enable signal. By disposing the sense amplifier in an inactive state early in response to a leading edge of the write enable pulse, improved writing efficiency can be achieved.

Abstract: A method for controlling an internal booster power source in an integrated circuit memory device including a plurality of voltage booster active kickers includes the steps of activating a first predetermined number of the voltage booster active kickers during a first voltage boost operation for the integrated circuit memory device, and activating a second predetermined number of the voltage booster active kickers during a second voltage boost operation for the integrated circuit memory device. In particular, the second predetermined number is greater than the first predetermined number. Furthermore, the plurality of voltage booster active kickers can include four booster active kickers and the first predetermined number can be two and the second predetermined number can be four. Related memory devices are also discussed.

Abstract: An integrated circuit memory device includes a main row decoder, a sub-row decoder, and a sub-word line driver. The main row decoder decodes the first portion of a row address, and generates a main row activation signal when one of the plurality of rows have been selected. The sub-row decoder decodes a second portion of the row address, and generates a first sub-row activation signal when a first one of the plurality of rows has been selected. The sub-row decoder generates a second sub-row activation signal when a second one of the plurality of rows has been selected. The sub-word line driver activates a first memory cell in the first row in response to the main row activation signal and the first sub-row activation signal. The sub-word line driver activates a second memory cell of the second row in response to the main row activation signal and the second sub-row activation signal.

Abstract: An integrated circuit memory device includes a plurality of memory cells arranged in an array of rows and columns, a plurality of word lines wherein each of the word lines is associated with a predetermined row of the memory cells, and a plurality of common lines wherein each of the column lines is associated with a predetermined column of the memory cells. Each of a plurality of sense amplifiers is associated with a respective column line and each of the sense amplifiers detects a voltage difference between a pair of bit lines for the respective column and amplifies the voltage difference. A row decoder selects one of the word lines in response to a row address input during a write operation. An input/output driver receives data input during the write operation, and each of a plurality of input/output gates is connected between the input/output driver and a respective one of the column lines.

Abstract: A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

Abstract: Disclosed is a layout method for increasing pitches between bit lines and between sense amplifiers so as to easily accomplish fabrication of a semiconductor memory device and a semiconductor memory array capable of reducing the number of sense amplifiers. The semiconductor memory array includes a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier being connected to each pair of the bit lines, wherein the sense amplifiers placed in each column make up each group, with odd pairs of the bit lines being connected to even or odd sense amplifier groups, and even pairs of the bit lines being connected to even or odd sense amplifier groups.

Abstract: A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise.

Abstract: A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.