Abstract: In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first coarse programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second coarse programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Abstract: A memory device includes word lines and a control circuit coupled to the word lines. The control circuit is configured to apply a programming voltage to a first word line of the word lines, apply a first pass voltage to a second word line of the word lines, apply a second pass voltage to a third word lines of the word lines, the second word line and the third word line are located on opposite sides of the first word line, apply a third pass voltage to a fourth word line of the word lines, the second word line is located between the fourth word line and the first word line, and apply a fourth pass voltage to a fifth word line of the word lines. The third word line is located between the fifth word line and the first word line. The first pass voltage is different from the third pass voltage. The second pass voltage is different from the fourth pass voltage.

Abstract: An example of the present disclosure disclose a memory comprising a memory array and a peripheral circuit coupled with the memory array. The memory array comprises a plurality of memory cells. The peripheral circuit is configured to: apply N program voltages to a word line coupled with a to-be-programmed memory cell with a target state being the highest state to perform a first program operation, to program the to-be-programmed memory cell with the target state being the highest state to a first threshold voltage, wherein a difference between a target threshold voltage corresponding to the to-be-programmed memory cell with the target state being the highest state and the first threshold voltage is less than a first preset value, and N is a positive integer; and apply M program voltages to the word line to perform a second program operation.

Abstract: A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.

Abstract: In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Abstract: The present disclosure provides a method for erasing a memory device. The method includes applying a word-line voltage to a word line of the memory device, wherein a first set of memory cells coupled to the word line are each configured to store a first number of bits data. The method also includes applying a hold voltage to a selected dummy line for a first time period, wherein a second set of memory cells coupled to the selected dummy line are each configured to store a second number of bits data less than the first number of bits data. The method further includes removing the hold voltage from the selected dummy line after the first time period such that an electric potential of the selected dummy line rises to a first voltage higher than the word-line voltage; and increasing the first time period incrementally in each of subsequent erase loops.

Abstract: Upon determining that a first read operation on one memory cell of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to second word line, and a first pass voltage is applied to third word line. The second word line include one or more word lines adjacent to a selected word line, and the third word line include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the second word line in the first read operation. The second pass voltage is higher than the first pass voltage.

Abstract: Examples of the present application disclose a memory device, a memory system, and an operation method of a memory device. In the method, prior to ISPP programming of memory cells of selected memory cells, a first preprogram pulse is first applied to a selected word line to preprogram a first class of memory cells of the selected memory cells.

Abstract: Example memory devices, memory systems, and methods for reducing time of program operation in NAND flash memory are disclosed. One example method includes programming a first memory cell in a first memory cell string of a memory cell array by applying a first programming voltage to a first word line coupled to the first memory cell string from a first time to a second time. A second programming voltage higher than or equal to the first programming voltage is applied to the first word line from the second time to a third time to program a second memory cell in a second memory cell string of the memory cell array, where the first word line is coupled to the second memory cell string.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Abstract: Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

Abstract: A memory device includes a memory string, and a control logic coupled to the memory string. The control logic is configured to perform a first programming operation and a second programming operation on a selected memory cell of the memory string, after the first programming operation and before the second programming operation, apply a ground voltage to a first word line coupled to the selected memory cell, and apply a first voltage to a second word line coupled to an unselected memory cell of the memory string, wherein the first voltage is higher than the ground voltage.

Abstract: Disclosure includes systems, methods and devices to program a memory device, involving a first and a second programming operations on a memory cell of the memory device. In the first programming operation, the memory cell is programmed into an intermediate state. In the second programming operation, the memory cell is programmed from the intermediate state into a target state. The first programming operation includes providing a bias voltage to a bit line coupled to the memory cell and providing a programming voltage to a word line coupled to the memory cell. An amplitude of the bias voltage provided to the bit line depends on the intermediate state or the target state the memory cell to be programmed into. Accordingly, no verification operation need to be performed on the memory cell in the first programming operation.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Abstract: The disclosure provides a programming method of a memory, a memory and a memory system, which relate to the technical field of semiconductor chips. The programming method comprises: applying a program voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; and during a stage of applying the program voltage to the first word line, applying a turn-on voltage to a first select line and a second select line sequentially, wherein the first select line is coupled to a select transistor of the first memory cell slice, and the second select line is coupled to a select transistor of the second memory cell slice.

Abstract: The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Abstract: The present disclosure provides a method of operating a memory, a memory, a memory system and an electronic device. In an example, a method of operating a memory is provided. The memory includes multiple word lines, and each of the plurality of word lines is coupled to a plurality of memory cells. The method includes: performing a first programming operation on a plurality of memory cells coupled to a selected word line among the multiple word lines, the first programming operation including applying a one-pulse to the selected word line to program the multiple memory cells coupled to the selected word line into N programmed states; and performing a second programming operation on the selected word line to program the multiple memory cells coupled to the selected word line into N target programmed states, where N is a positive integer.