Abstract: The present disclosure provides a configuration method and a reading method for a 3D memory, a 3D memory and system. The configuration method includes: writing test data into a plurality of selected memory cells corresponding to a selected word line in one of a plurality of memory blocks of the memory device; determining threshold voltages of the plurality of selected memory cells; and obtaining a relationship table indicating a corresponding relationship between a number of a subset of the selected memory cells that have threshold voltages lower than a preset voltage and a pass voltage required for performing a read operation on the one memory block.

Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.

Abstract: A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Abstract: A medium-deep non-interference geothermal heating system based on loose siltstone geology includes a water return pipe and a water inlet pipe. The system further includes a differential pressure overflow pipe, a gauge, a differential pressure controller, a first high area water return pipe, a first water return pipe, a third water return pipe, a bypass pipe, a high area water supply pipe, a second high area water return pipe, a geothermal well water return pipe, a geothermal well water supply pipe, a heat pump unit, a second water return pipe, a water supply pipe, a geothermal well water pump, a first geothermal well water supply pipe, a first geothermal well water return pipe, a second geothermal well water return pipe, a second geothermal well water supply pipe, a geothermal wellhead device, and a geothermal well that are combined for use.

Abstract: A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.

Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Abstract: Disclosed herein is a reservoir isolation valve for secondary completion, which includes a shell assembly, a sleeve assembly arranged in the shell assembly, a reset spring arranged between the shell assembly and the sleeve assembly, a movable tube, an inner limit tube, an outer limit tube, an outer bearing socket, an inner bearing socket, a thrust bearing, a ball valve arranged in the sleeve assembly, a stepped shaft fixed on the ball valve, a transmission mechanism configured for connecting the movable tube to the stepped shaft and allowing the stepped shaft to rotate and a startup part.

Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.

Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Abstract: An electrical connector includes a connector housing and a plurality of conductive terminals mounted in the connector housing. The plurality of conductive terminals include a plurality of ground terminals and a plurality of signal terminals. The ground terminals and the signal terminals are each made of a lossy metal. A surface of each of the signal terminals is coated with a low lossy metal.

Abstract: A connector housing includes a receiving chamber having a pair of opposite side walls, a support rib disposed in a lower portion of the receiving chamber and extending in the longitudinal direction, a row of first receiving compartments disposed in each of the pair of opposite side walls of the receiving chamber, and a partition wall disposed between each pair of adjacent first receiving compartments. The receiving chamber extends in a longitudinal direction and a height direction and is adapted to receive a mating connector. The row of first receiving compartments face the support rib and position a plurality of conductive terminals. Each partition wall extends from an outer side of the first receiving compartments in a lateral direction and is connected to the support rib. At least one of the partition walls is at least partially cut away.

Abstract: A cable detection apparatus includes a cable support and a vision system. The vision system has a camera device rotatable about an axis parallel to an axial direction of a cable to be detected, so as to capture an image of the cable, and an optical element rotated synchronously with the camera device. The optical element transmits the image of the cable to the camera device by changing an optical path of the image.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.

Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.

Abstract: A medium-deep non-interference geothermal heating system based on loose siltstone geology includes a water return pipe and a water inlet pipe. The system further includes a differential pressure overflow pipe, a gauge, a differential pressure controller, a first high area water return pipe, a first water return pipe, a third water return pipe, a bypass pipe, a high area water supply pipe, a second high area water return pipe, a geothermal well water return pipe, a geothermal well water supply pipe, a heat pump unit, a second water return pipe, a water supply pipe, a geothermal well water pump, a first geothermal well water supply pipe, a first geothermal well water return pipe, a second geothermal well water return pipe, a second geothermal well water supply pipe, a geothermal wellhead device, and a geothermal well that are combined for use.

Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.

Abstract: An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: Disclosed herein is a reservoir isolation valve for secondary completion, which includes a shell assembly, a sleeve assembly arranged in the shell assembly, a reset spring arranged between the shell assembly and the sleeve assembly, a movable tube, an inner limit tube, an outer limit tube, an outer bearing socket, an inner bearing socket, a thrust bearing, a ball valve arranged in the sleeve assembly, a stepped shaft fixed on the ball valve, a transmission mechanism configured for connecting the movable tube to the stepped shaft and allowing the stepped shaft to rotate and a startup part.