Abstract: Provided a genetically modified yeast strain for producing succinic acid, which strain has the activity or an enhanced activity of an NADPH-dependent malate dehydrogenase (EC 1.1.1.82), and optionally also has the activity or an enhanced activity of at least one of the following: (i) soluble fumarate reductase (EC 4.2.1.2), (ii) a pyruvate carboxylase (EC 6.4.1.1), (iii) a fumarase (EC 4.2.1.2), and (iv) succinate transport protein; and a preparation method therefor, a method for producing succinic acid using same, and the use thereof.

Abstract: The present invention provides a genetically modified malic acid producing yeast strain, wherein the strain has or has enhanced malate transport protein activity and has or has enhanced NADPH-dependent malate dehydrogenase (EC 1.1.1.82) activity, optionally also has or has enhanced at least one of the following activities: (i) pyruvate carboxylase (EC 6.4.1.1) activity, (ii) phosphoenolpyruvate carboxykinase (EC 4.1.1.49) activity, (iii) phosphoenolpyruvate carboxylase activity, and (iv) biotin transport protein activity; and a preparation method thereof, a method for producing L-malic acid using the same, and use thereof.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R6, m and n are I a described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface to be subjected to a roughness treatment to form an uneven morphology on the first surface; forming a surface treatment layer, wherein the surface treatment layer has an uneven surface morphology; and forming a polysilicon layer on the surface treatment layer. By the roughness treatment to the first substrate, the first surface and the surface treatment layer both have uneven surface morphology, such that the formed polysilicon layer has stable orientation evolution and grain size, and an increased grain boundary density. Thereby a highly efficient charge trapping polysilicon film can be obtained.

Abstract: The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface, and a pinning layer is formed on the first surface by a deposition process, and homogenizing the pinning layer surface by dry etching to adjust a thickness uniformity of the pinning layer. Accordingly, the thickness uniformity of the obtained polysilicon film is able to reach a good state.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3, A1 to A3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon.

Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Abstract: The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3, m and n are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I), wherein R1 and R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I) and pharmaceutically acceptable salts thereof. The compounds act as antagonists of the toll-like receptors TLR7, TLR8 and/or TLR9 and are thus useful in the treatment of systemic lupus erythematosus (SLE) and lupus nephritis.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I), wherein R1, R2 and R3 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds as antagonist of TLR7 and/or TLR8 and/or TLR9 in the treatment of autoimmune diseases as well as auto-inflammation diseases.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.