Abstract: An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.

Abstract: In one embodiment, an apparatus comprising a first resistor, the first resistor comprising a first type of resistor having a plurality of metal wires in respective layers, the plurality of metal wires arranged in series via a plurality of vias.

Abstract: An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.

Abstract: An electronic apparatus including an oscillator, a sampler, a phase detector, a phase rotator and a loop filter is provided. The oscillator generates a reference and an auxiliary clock signal offset by 90 degrees. The sampler samples an input data signal at each transition edges to generate primary sampled signals. The phase detector determines a phase difference of a data transition of the input data signal relative to a data-sampling edge. The phase rotator rotates the primary sampled signals and the reference clock signal according to the phase difference. The loop filter generates a control voltage to control the oscillator to vary phases of the reference clock signal and the auxiliary clock signal according to phase difference of the data transition relative to the rotated reference clock signal.

Abstract: In one embodiment, an apparatus comprising a first resistor, the first resistor comprising a first type of resistor having a plurality of metal wires in respective layers, the plurality of metal wires arranged in series via a plurality of vias.

Abstract: A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.

Abstract: A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell.

Abstract: A temperature invariant digitally controlled oscillator is disclosed. The digitally controlled oscillator is configured to generate an output clock with stable frequency. The temperature invariant digitally controlled oscillator comprises a digitally controlled oscillator, a temperature sensor, a temperature decision logic circuit, and a temperature conditioner. The digitally controlled signal is provided to adjust the oscillation frequency of the digitally controlled oscillator by changing its capacitances. The stabilization of the silicon temperature is achieved with the temperature sensor, the temperature decision logic circuit, and the temperature conditioner.

Abstract: A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted.

Abstract: A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code.

Abstract: Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor.

Abstract: Systems and methods for generating spectrally shaped pseudo random noise sequences are described, which may include generating an L-level PN sequence, where L is an integer greater than 1; up-sampling the PN sequence by a factor of M, where M is an integer greater than 1; and filtering the up-sampled PN sequence using a finite impulse response (FIR) filter of length M, where the coefficients of the FIR filter are chosen from a set of pre-determined values.

Abstract: A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.

Abstract: A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

Abstract: A low flicker noise active mixer comprises a trans-conductance section, a switching quad, and a load section. The trans-conductance section converts a voltage signal pair into a first current signal pair. The switching quad converts the first current signal pair into a second signal pair in a manner controlled by a LO (local oscillator) signal pair. The load section provides a loading to the second current signal pair using a pair of commutative active loads to convert the second current signal pair into an output voltage signal pair.

Abstract: Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor.

Abstract: A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

Abstract: An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.

Abstract: A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted.

Abstract: A temperature invariant digitally controlled oscillator is disclosed. The digitally controlled oscillator is configured to generate an output clock with stable frequency. The temperature invariant digitally controlled oscillator comprises a digitally controlled oscillator, a temperature sensor, a temperature decision logic circuit, and a temperature conditioner. The digitally controlled signal is provided to adjust the oscillation frequency of the digitally controlled oscillator by changing its capacitances. The stabilization of the silicon temperature is achieved with the temperature sensor, the temperature decision logic circuit, and the temperature conditioner.