Abstract: A hybrid coarse-fine time-to-digital converter is disclosed. The hybrid coarse-fine time-to-digital converter is configured to receive a first input signal and a second input signal and to generate a digital output that corresponds to the time difference of between a rising edge of the first input signal and a rising edge of the second input signal. The hybrid coarse-fine time-to-digital converter comprises a coarse time-to-digital converter, a fine time-to-digital converter, and a correlated output generator.

Abstract: An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.

Abstract: An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.

Abstract: A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell.

Abstract: A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal.

Abstract: A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.

Abstract: An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.

Abstract: A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code.

Abstract: A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

Abstract: A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.

Abstract: A tuning circuit element for a tuning circuit. The tuning circuit element may include sub-elements for generating circuit values depending on logical values of digital control input signals. The tuning circuit element may be implemented with varactors, current sources, and other components or circuits. The tuning circuit element may be configured to have fine tuning resolution that is not necessarily limited by minimum feature size of a given fabrication process technology.

Abstract: A low flicker noise active mixer comprises a trans-conductance section, a switching quad, and a load section. The trans-conductance section converts a voltage signal pair into a first current signal pair. The switching quad converts the first current signal pair into a second signal pair in a manner controlled by a LO (local oscillator) signal pair. The load section provides a loading to the second current signal pair using a pair of commutative active loads to convert the second current signal pair into an output voltage signal pair.

Abstract: A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

Abstract: A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal.

Abstract: Systems and methods for generating spectrally shaped pseudo random noise sequences are described, which may include generating an L-level PN sequence, where L is an integer greater than 1; up-sampling the PN sequence by a factor of M, where M is an integer greater than 1; and filtering the up-sampled PN sequence using a finite impulse response (FIR) filter of length M, where the coefficients of the FIR filter are chosen from a set of pre-determined values.

Abstract: A self-calibrating continuous-time delta-sigma modulator determines whether time constants of its internal integrators are too large or too small by injecting a calibrating sequence into the modulator and examining a correlation between the calibrating sequence and a modulator output sequence. Then the time constants of the internal integrators are adjusted accordingly. In one embodiment, the correlation is exploited based on matching a noise transfer function of the modulator using an adaptive filter based on a least mean square (LMS) algorithm.

Abstract: A primary delta-sigma modulator converts a continuous-time input signal into a discrete-time output sequence. A calibration circuit comprising an auxiliary delta-sigma modulator estimates percentage error in an integrator time constant and adjusts the time constant of at least one integrator in the primary delta-sigma modulator accordingly. The auxiliary delta-sigma modulator and the primary delta-sigma modulator use integrators with substantially similar circuit designs. The percentage error in the time constant of the integrator in the auxiliary delta-sigma modulator, and correspondingly the percentage error in time constant of the integrator in the primary delta-sigma modulator, is estimated by injecting a calibrating sequence into the auxiliary delta-sigma modulator and examining a correlation between an error sequence and an output sequence of the auxiliary delta-sigma modulator.

Abstract: In one embodiment, a phase-locked loop system in a receiver samples received incoming data using a first clock and a second clock that have the same frequency but are out of phase with each other. A first control signal generated by a phase detector is used to control a charge pump, whose output may be filtered to drive a VCO circuit generating the first and second clocks. A frequency detector generates a second control signal based at least on phase relationships between the incoming data and the first and second clocks. A qualifier circuit determines if the first control signal is valid or invalid based at least on the second control signal. If the first control signal is invalid, the qualifier circuit prevents the first control signal from being used to adjust the frequency of the first and second clocks.

Abstract: A self-calibrating continuous-time delta-sigma modulator determines whether time constants of its internal integrators are too large or too small by injecting a calibrating sequence into the modulator and examining a correlation between the calibrating sequence and a modulator output sequence. Then the time constants of the internal integrators are adjusted accordingly. In one embodiment, the correlation is exploited based on matching a noise transfer function of the modulator using an adaptive filter based on a least mean square (LMS) algorithm.

Abstract: A primary delta-sigma modulator converts a continuous-time input signal into a discrete-time output sequence. A calibration circuit comprising an auxiliary delta-sigma modulator estimates percentage error in an integrator time constant and adjusts the time constant of at least one integrator in the primary delta-sigma modulator accordingly. The auxiliary delta-sigma modulator and the primary delta-sigma modulator use integrators with substantially similar circuit designs. The percentage error in the time constant of the integrator in the auxiliary delta-sigma modulator, and correspondingly the percentage error in time constant of the integrator in the primary delta-sigma modulator, is estimated by injecting a calibrating sequence into the auxiliary delta-sigma modulator and examining a correlation between an error sequence and an output sequence of the auxiliary delta-sigma modulator.