Abstract: A device includes a first processor and a second processor. The first processor is configured to operate in accordance with a first power mode. The first processor includes a first transistor. The first processor is configured to, while operating in accordance with the first power mode, switch the first transistor at a first duty cycle. The second processor is configured to operate in accordance with a second power mode. The second processor includes a second transistor. The second processor is configured to, while operating in accordance with the second power mode, switch the second transistor at a second duty cycle. The second duty cycle is greater than the first duty cycle. The second processor consumes less power while operating in accordance with the second power mode than the first processor consumes while operating in accordance with the first power mode.

Abstract: A system comprising a processor, a first cache, and a second cache. The processor is configured to perform a processing task according to data stored in a main memory and output a command associated with the processing task. The first cache is located between the processor and the main memory and is configured to store a first portion of the data stored in the main memory and provide a first indication of whether the command has been completed at the first cache. The second cache is located between the first cache and the main memory and is configured to store a second portion of the data stored in the main memory and provide a second indication of whether the command has been completed at the second cache. The processor is configured to perform the processing task in response to receiving both the first indication and the second indication.

Abstract: Disclosed are a beamformer and a beamforming method. The beamformer includes a plurality of dividers, each of which divides an input signal along a plurality of paths, an input switch which selects one of the dividers such that the input signal is input to the selected divider, a phase shifter which shifts phases of respective output signals from the divider, and an output switch which transmits the output signals from the phase shifter to an antenna.

Abstract: A processing device including first processors, second processors, a first chipset, and a second chipset. The first chipset is in communication with the first processors via a first bus. The second chipset is in communication with the first chipset via a second bus and is directly connected to the second processors. The first chipset and the second chipset are connected between (i) the first processors and (ii) a first non-volatile memory and a second non-volatile memory. The second chipset is connected between (i) the second processors and (ii) the first non-volatile memory and the second non-volatile memory. The first processors access the first non-volatile memory during a first power mode. The second processors access the second non-volatile memory during a second power mode that is different than the first power mode.

Abstract: A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time. The processor causes data associated with the first processor thread to pass through the processor's pipeline during the first periods of processor time. A second counter is similarly configured. The processor can be configured to receive an input defining processor time to be allocated to one or more processor threads and to use the input to change one or more of the counters such that subsequent periods of processor times for the one or more processor threads are affected.

Abstract: A method and an apparatus for determining a projection area of an image are provided. The method for determining a projection area of an image, comprises: an input step of inputting an image sequence having a plurality of images; a detecting step of detecting locations of projection areas of the respective images in the image sequence; a relationship classification judging step of judging a relationship classification between the image and a previous image before the image being projected based on a relationship between the location of the projection area of the image and the location of the projection area of the previous image; and a determining step of determining the locations of the projection areas of the respective images based on the relationship classification judged in the relationship classification judging step.

Abstract: Disclosed are an object detection method and an object detection device. The object detection method comprises a step of obtaining plural detection results of a current frame according to plural object detection methods; a step of setting initial probabilities of the plural detection results of the current frame; a step of calculating a movement frequency distribution diagram representing movement frequencies of respective pixels in the current frame; a step of obtaining detection results of a previous frame; a step of updating the probabilities of the plural detection results of the current frame; and a step of determining a final list of detected objects based on the updated probabilities of the plural detection results of the current frame.

Abstract: A system including a processor, a first-in first-out (FIFO) module, and an arbiter module. The processor includes i) a processor core and ii) a memory. The FIFO module is configured to receive streaming data, output the streaming data to the memory of the processor, and selectively generate a control signal. The arbiter module is configured to adjust, based on the control signal, a priority in which at least one of the processor core and the FIFO module accesses the memory of the processor.

Abstract: Method and apparatus for controlling bias point of DQPSK demodulator are disclosed. The method comprises: step 1: respectively applying first and second bias voltages to I-path and Q-path, and applying identical pilot voltage signals to I-path and Q-path (S202); step 2: executing filtering processing on I-path and Q-path differential current signals collected by balance receiver and determining ?Iand ?Q (S204); step 3: performing feedback control to first and second bias voltages respectively according to ?I and ?Q so that ?I and ?Q respectively reaches expected bias point values of I-path and Q-path (S206); executing step 2 and 3 cyclically at preset regular intervals (S208), so that ?I and ?Q remains consistently the expected bias point values of I-path and Q-path. The solution enables bias point of DQPSK demodulator to be locked at any expected bias point value, facilitates realization of digitization, and is not easily influenced.

Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

Abstract: The present invention provides a method and an apparatus for controlling a phase delay offset point of a modulator. The method comprises: acquiring backlight detection current signals output from a modulator in different working states, and determining harmonic amplitude values of the backlight detection current signals corresponding to the different working states; determining a detection value of a phase delay offset point corresponding to the modulator according to the determined harmonic amplitude values; comparing the detection value with a set target value of the phase delay offset point, and controlling a position of the phase delay offset point corresponding to the modulator according to the comparison result. The accuracy of controlling the position of the phase delay offset point of the modulator and the performance of the Differential Quadrature Phase Shift Keying (DQPSK) modulation system are improved through the technical solution.

Abstract: The disclosure discloses a method and an apparatus for determining a bias point of a modulator, wherein the method includes: adding pilot signals to the bias voltages of the modulator; adjusting the bias point of the modulator at a predetermined step and acquiring a first harmonic amplitude value corresponding to each bias point in a backlight detection current signal output by the modulator; and determining a bias point corresponding to the maximum value of the first harmonic amplitude values associated with multiple bias points as the bias point of the modulator. By virtue of the disclosure, the detection of a difference frequency signal can be eliminated, thereby reducing the complexity and cost of a periphery control circuit while ensuring the control accuracy, effectively improving the stability and reliability of the control process, and improving the modulation and transmission performance of optical signals in the whole system.

Abstract: A computer mouse includes a housing and a button assembly. The button assembly includes a button, a circuit board, a first conductive sheet, and a second conductive sheet. The button is exposed out of the housing. The circuit board is received in the housing, and includes a first contact and a second contact. The first conductive sheet has a first magnet fixed thereon, and is electrically connected to the first contact of the circuit board. The second conductive sheet is electrically connected to the second contact of the circuit board. The second conductive sheet is fixed to the button and contactable with the first conductive sheet when the button is pressed. The second magnet and the first magnet form a repulsive force therebetween.

Abstract: A computer cache for a memory comprises a data random-access memory (RAM) containing a plurality of cache lines. Each of the cache lines stores a segment of the memory. A tag RAM contains a plurality of address tags that correspond to the cache lines. A valid RAM contains a plurality of validity values that correspond to the cache lines. The valid RAM is stored separately from the tag RAM and the data RAM. The valid RAM is selectively independently clearable. A hit module determines whether data is stored in the computer cache based upon the valid RAM and the tag RAM.

Abstract: A diaphragm pump includes a motor, an eccentric member driven by the motor, and a diaphragm. The motor includes an output shaft connected with the eccentric member. The eccentric member includes multiple arms which move up and down due to the rotation of the output shaft. The diaphragm has multiple bladders. Each bladder forms a pump chamber. The bladders are connected with the arms such that the bladders are compressed or expanded due to the movement of the arms. The pump has an air exhaust chamber and an air inlet chamber. The air inlet chamber is connected to the pump chambers via a passage. The passage includes a cavity which overlaps the air exhaust chamber in an axial direction of the motor.

Abstract: An input/output (I/O) interface blocking device includes a fitting member. The fitting member includes a protruding portion, which includes a first sidewall and a second sidewall opposite to each other. The first sidewall is slanted in a direction allowing the first fitting member to be inserted into a space in an I/O interface receptacle. The second sidewall is configured to block the fitting member from being pulled out of the space in the I/O interface receptacle.

Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

Abstract: A gas releasable key structure including a base, a thin-film circuit, a key cap and an elastic structure is disclosed. The elastic structure is disposed between the key cap and the thin-film circuit and includes a cap body, a ring-shaped flange, a motion pillar and a conductor. The cap body has a first opening and a second opening. The ring-shaped flange connects an edge around the first opening. The motion pillar in the cap body has a through hole, an upper surface and a lower surface. The through hole is extended to the upper surface from the lower surface, connecting the second opening. The conductor on the lower surface has an indent and a breach that connects the through hole. When the first opening is closed, the gas inside the cap body is dissipated to the exterior via the indent, the breach, the through hole and the second opening.