Abstract: Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time. The processor causes data associated with the first processor thread to pass through the processor's pipeline during the first periods of processor time. A second counter is similarly configured. The processor can be configured to receive an input defining processor time to be allocated to one or more processor threads and to use the input to change one or more of the counters such that subsequent periods of processor times for the one or more processor threads are affected.

Abstract: An onion waveform generator and a spread spectrum clock generator (SSCG) using the same are provided. The onion waveform generator includes a value generation unit and an accumulating unit. The value generation unit outputs a counting value. The accumulating unit accumulates the counting value to output a waveform value. The accumulating unit switches from an increasing mode to a decreasing mode if the waveform value is a third boundary value, and the accumulating unit switches from the decreasing mode to the increasing mode if the waveform value is a fourth boundary value.

Abstract: A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.

Abstract: Another embodiment of the invention provides a data saving system including a portable device having a first data, a third party and a storage management server. The storage management server connects at least one backup device, wherein when the portable device wants to save the first data, the portable device transmits the first data and a save command to the third party, the storage management server monitors the third party to determine whether there is data designated to the storage management server, and if yes, the storage management server acquires and transmits the first data to the backup device.

Abstract: A disk drive system-on-chip (SOC) includes a read-channel module and a processor. The read-channel module reads data, includes a first error-correcting module for correcting errors in the data, corrects errors in a first portion of the data using the first error-correcting module, and is unable to correct errors in a second portion of the data using the first error-correcting module. The processor includes a processor core and processor memory, receives the second portion of the data in the processor memory, and corrects errors in the second portion of the data using a second error-correcting module that is different than the first error-correcting module.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

Abstract: The present innovation discloses a network communication establishment method between a portable device and a computer. The major feature of the present innovation is that the parameters are transmitted via the email and after the connection is established, the commands or requests for data transmission are still transmitted via email. As to the data under transmission, it is transmitted by peer to peer (P2P) technology. In another embodiment, the data may also be transmitted via email.

Abstract: The present invention discloses a data transmission method for a first electronic device and a second electronic device. The method includes the steps of finding a first available port of the first electronic device, finding a second available port of the second electronic device, transforming a first data into a second data, wherein a format of the second data is an XML format, and transmitting the second data to the first electronic device or the second electronic device via the first available port or the second available port.

Abstract: A method of synthesizing polyethyleneimine with a substantially linear backbone is disclosed. The method comprises exposing ethylenediamine dissolved in a solution to electromagnetic radiation for a sufficient time to polymerize the ethylenediamine and thereby resulting in formation of polyethylenimine with a substantially linear backbone in the solution. A method of synthesizing a homopolymer with a substantially linear backbone is also disclosed. In addition, a composition comprising polyethylenimine synthesized from the aforementioned method is disclosed, in which the polyethylenimine comprises a backbone conformation that is substantially linear and has a distribution of molecular weights (MW) ranging from 1 kDa to 200 kDa; and the polyethyleneimine has no cytotoxicity at a concentration of 12 ?g/ml.

Abstract: A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

Abstract: A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.

Abstract: A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T?1 bits, the source index input identifying one of a plurality of unbanked registers; receiving a processor mode input to identify one of P processor modes, where P is greater than two; generating an encoded address having a length of T bits based on the source index input and the processor mode input; and identifying one of the plurality of unbanked registers associated with one of the P processor modes using the encoded address.

Abstract: In one implementation, a pipeline processor is provided having a base architecture that includes one or more decoders operable to decode program instructions and generate one or more decoded instructions, and one or more execution units operable to execute the one or more decoded instructions. Each execution unit includes one or more execution pipeline stages. The pipeline processor architecture further includes one or more additional co-processor pipelines. The one or more decoders of the base architecture are operable to recognize one or more instructions to be processed by a given co-processor pipeline and pass the one or more recognized instructions to the given co-processor pipeline for decoding and execution.

Abstract: Disclosed are an object detection method and an object detection device. The object detection method comprises a step of obtaining plural detection results of a current frame according to plural object detection methods; a step of setting initial probabilities of the plural detection results of the current frame; a step of calculating a movement frequency distribution diagram representing movement frequencies of respective pixels in the current frame; a step of obtaining detection results of a previous frame; a step of updating the probabilities of the plural detection results of the current frame; and a step of determining a final list of detected objects based on the updated probabilities of the plural detection results of the current frame.

Abstract: A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

Abstract: A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.

Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

Abstract: The present invention relates to a white and color photoexcitation light emitting sheet comprising a substrate, a light source formed on the substrate, and a white and color photoexcitation light emitting layer capable of converting a light emitted from the light source into a light having a different wavelength, where the white and color photoexcitation light emitting layer is fabricated by mixing a matrix polymer, white and color photoexcitation light emitting materials and a solvent, spinning the resulting mixture to prepare an ultrafine composite fiber layer of the matrix polymer/photoexcitation light emitting materials, and thermocompressing the ultrafine composite fiber layer; and a method for fabrication thereof. The white and color photoexcitation light emitting sheet according to the present invention has uniform brightness and color coordinates and exhibits high color reproducibility.