Patents by Inventor Hongbin Zhu

Hongbin Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020566
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a structure extending vertically through the memory stack, a first dielectric layer on the memory stack, an etch stop layer on the first dielectric layer, a second dielectric layer on the etch stop layer, a first contact through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure, and a second contact through the second dielectric layer and in contact with at least an upper end of the first contact.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 21, 2021
    Inventors: Hongbin Zhu, Juan Tang, Zi Qun Hua
  • Publication number: 20210020653
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The slit structure extends vertically through the memory stack. An upper end of the slit structure is above an upper end of the channel structure.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 21, 2021
    Inventors: Hongbin Zhu, Juan Tang, Wei Xu
  • Publication number: 20210003008
    Abstract: A mine field layout method suitable for fluidized mining of coal resources is provided. A main shaft and an air shaft are provided in the mine field, the bottom of the main shaft is located in the shallow horizontal coal seam zone, and the bottom of the air shaft is located in the deep horizontal coal seam zone. The horizontal main roadways are arranged at two boundaries along the strike of the coal seam, and inclined main roadways are arranged at two boundaries along the dip direction of the coal seam. Connecting roadways are located inside the mine field and are in communication with the horizontal main roadways. In the coal mining stage, the coal resources can be converted into the fluidized energy product and/or electricity by an unmanned automatic mining machine.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 7, 2021
    Applicants: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, BEIJING, SHENZHEN UNIVERSITY
    Inventors: Yang JU, Heping XIE, Yong ZHANG, Yan ZHU, Feng GAO, Xiaodong NIE, Changbing WAN, Jinxin SONG, Chang LU, Hongbin LIU, Zhangyu REN
  • Patent number: 10879259
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Patent number: 10879254
    Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 29, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
  • Patent number: 10834399
    Abstract: Embodiments of the present application disclose a compression method and device of a panoramic video. The method comprises: for a target panoramic video, generating each frame picture of the target panoramic picture; for each frame picture respectively, compressing the frame picture; dividing the compressed frame picture; mosaicking the pictures obtained through the dividing; generating a new panoramic video according to all the pictures obtained through the mosaicking. With the embodiments of the present application, waste of network bandwidth can be reduced.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 10, 2020
    Assignee: BEIJING QIYI CENTURY SCIENCE & TECHNOLOGY CO. LTD.
    Inventors: Tao Wang, Jiadan Zhu, Yao Du, Hongbin Liu
  • Patent number: 10818631
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 27, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10811380
    Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: October 20, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
  • Patent number: 10787754
    Abstract: The present invention relates to a polymer/filler/metal composite fiber, including a polymer fiber comprising a metal short fiber and a filler; the metal short fiber is distributed as a dispersed phase within the polymer fiber and distributed in parallel to the axis of the polymer fiber; the filler is dispersed within the polymer fiber and distributed between the metal short fibers; the filler does not melt at the processing temperature of the polymer; said metal is a low melting point metal and selected from at least one of single component metals and metal alloys, and has a melting point which ranges from 20 to 480° C., and, at the same time, which is lower than the processing temperature of the polymer; the metal short fiber and the polymer fiber have a volume ratio of from 0.01:100 to 20:100; the filler and the polymer have a weight ratio of from 0.1:100 to 30:100.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: September 29, 2020
    Assignees: China Petroleum & Chemical Corporation, Beijing Research Institute of Chemical Industry, China Petroleum & Chemical Corporation
    Inventors: Jinliang Qiao, Yilei Zhu, Xiaohong Zhang, Liangshi Wang, Chuanlun Cai, Guicun Qi, Hongbin Zhang, Zhihai Song, Jinmei Lai, Binghai Li, Ya Wang, Xiang Wang, Jianming Gao, Gang Chen, Haibin Jiang
  • Patent number: 10790297
    Abstract: Embodiments of methods for forming channel holes in 3D memory devices using a nonconformal sacrificial layer are disclosed. In an example, a dielectric stack including interleaved first dielectric layers and second dielectric layers is formed on a substrate. An opening extending vertically through the dielectric stack is formed. A nonconformal sacrificial layer is formed along a sidewall of the opening, such that a variation of a diameter of the opening decreases. The nonconformal sacrificial layer and part of the dielectric stack abutting the nonconformal sacrificial layer are removed. A channel structure is formed in the opening after removing the nonconformal sacrificial layer and part of the dielectric stack.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 29, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Baoyou Chen, Weihua Cheng, Hai Hui Huang, Zhuqing Huang, Guanping Wu, Hongbin Zhu, Yu Qi Wang
  • Patent number: 10741390
    Abstract: A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 11, 2020
    Assignee: Yangtz Memory Technologies Co., Ltd.
    Inventors: Haifeng Guo, Xiaojin Wang, Hongbin Zhu, Lin Lai, Teng Cheng, Lihong Xiao
  • Patent number: 10730851
    Abstract: The application discloses five polymorph forms B, P, F, J, O of (4-((R)-((2S,5R)-4-(3-fluorobenzyl)-(2,5-dimethylpiperazine-1-yl)(3-hydroxyphenyl)methyl)phenyl)(4-methylpiperidine-1-yl)methanone dihydrochloride, preparation methods thereof and application thereof in the manufacture of a medicament for preventing or treating a mood disorder or a disease related to a ? opioid receptor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 4, 2020
    Assignee: Yunnan Institute of Materia Medica
    Inventors: Jingkun Wang, Zhaoyun Zhu, He Song, Min Sun, Tao Cui, Zeren Wang, Zhi Yang, Min Su, Hongbin Liu, Bing Shi, Yong Mao, Huilang Liu, Zeqian Li, Chunmei Zhao, Mei Su, Fang Yuan, Tiancai Zhang, Yong Liu, Kuanren Zhang, Yunlin Wei, Yuehai Shen
  • Publication number: 20200243677
    Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
  • Publication number: 20200227427
    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
  • Publication number: 20200222583
    Abstract: Provided are novel biocompatible copolymers, compositions comprising the copolymers, and methods of using the copolymers. The copolymers are non-toxic and typically have an LCST below 37° C. Compositions comprising the copolymers can be used for wound treatment, as a cellular growth matrix or niche and for injection into cardiac tissue to repair and mechanically support damaged tissue. The copolymers comprise numerous ester linkages so that the copolymers are erodeable in situ. Degradation products of the copolymers are soluble and non-toxic. The copolymers can be amine-reactive so that they can conjugate with proteins, such as collagen. Active ingredients, such as drugs, can be incorporated into compositions comprising the copolymers.
    Type: Application
    Filed: February 19, 2020
    Publication date: July 16, 2020
    Inventors: Hongbin Jiang, William R. Wagner, Tomo Yoshizumi, Yang Zhu
  • Patent number: 10707121
    Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: July 7, 2020
    Assignee: Intel Corporatino
    Inventors: Jun Liu, Mark A. Levan, Gordon A. Haller, Fei Wang, Wei Yeeng Ng, Wesley O. McKinsey, Zhiqiang Xie, Jeremy F. Adams, Hongbin Zhu, Jun Zhao
  • Publication number: 20200212065
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Publication number: 20200208264
    Abstract: This invention relates to a semiconductor processing apparatus and a control method thereof. The semiconductor processing apparatus includes a processing chamber including two or more reaction regions. Each of the reaction regions includes an independent gas path module. The control method includes: cycle periods of introducing gas into the reaction regions are synchronized during the semiconductor processing. The semiconductor processing apparatus and the control method thereof of this invention can control the cycle periods of the reaction gas introduced into the reaction regions to be in consistent, so that the gas introduced into different reaction regions is the same at the same time, and the interference of the gas between the reaction regions is avoided, thereby improving the product yield.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 2, 2020
    Inventors: Hao PENG, Zhao LI, Hongbin ZHU, Xianjin WAN, Yuan LI, Feng ZHOU, Kai HU, Jun WEI, Xiangying CAI, Yao HU
  • Publication number: 20200194385
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Publication number: 20200176466
    Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.
    Type: Application
    Filed: December 22, 2018
    Publication date: June 4, 2020
    Inventors: Shengwei Yang, Zhongyi Xia, Kun Han, Kang Li, Xiaoguang Wang, Hongbin Zhu