Patents by Inventor Honglin Guo

Honglin Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784193
    Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
  • Publication number: 20200251440
    Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Patent number: 10629562
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
  • Publication number: 20200096574
    Abstract: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 26, 2020
    Inventors: Xiong LI, William TOTH, Honglin GUO, Danyang ZHU
  • Publication number: 20200035598
    Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventors: QI-ZHONG HONG, HONGLIN GUO, BENJAMIN JAMES TIMMER, GREGORY BOYD SHINN
  • Publication number: 20190206828
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 4, 2019
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Publication number: 20180102216
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Inventors: Honglin Guo, Byron Lovell Williams
  • Patent number: 9875846
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Byron Lovell Williams
  • Patent number: 9793106
    Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Tim A. Taylor, Jeff A. West, Ricky A. Jackson, Byron Williams
  • Publication number: 20160163452
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Honglin Guo, Byron Lovell Williams
  • Publication number: 20160133580
    Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.
    Type: Application
    Filed: September 15, 2015
    Publication date: May 12, 2016
    Inventors: Thomas D. Bonifield, Jeffrey A. West, Byron Williams, Honglin Guo
  • Publication number: 20160133689
    Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 12, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Tim A. Taylor, Jeff A. West, Ricky A. Jackson, Byron Williams
  • Patent number: 9293254
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: March 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Byron Lovell Williams
  • Publication number: 20150348708
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Texas Instrument Incorporated
    Inventors: Honglin Guo, Byron Lovell Williams
  • Patent number: 7888776
    Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
  • Publication number: 20100276039
    Abstract: Copper alloys, methods for producing copper alloys, and copper tubes are provided. The copper alloys include an alpha solid solution formed from phosphorous deoxidized copper and at least one trace element comprising tin. The content of tin ranges from about 0.1% to about 2.0% by weight of the copper alloy. The trace element can further include zinc in an amount from about 0.05% to about 1.0% by weight of the copper alloy. The copper alloys have an increased tensile strength due to the strengthening effect by the alpha solid solution formed by phosphorous deoxidized copper and tin as the trace element, and accordingly a copper tube made from the copper alloy has a significantly improved pressure resistance.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 4, 2010
    Applicant: Golden Dragon Precise Copper Tube Group Inc.
    Inventors: Honglin Guo, Zhenguo Feng, Jinhao Zhao, Daixing Liu, Guowei Liu, Junqi Li
  • Publication number: 20090321734
    Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
  • Patent number: 7612454
    Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Honglin Guo, Dongmei Lei, Brian Goodlin, Joe McPherson
  • Publication number: 20080265366
    Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.
    Type: Application
    Filed: July 14, 2008
    Publication date: October 30, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Honglin Guo, Dongmei Lei, Brian Goodlin, Joe McPherson
  • Patent number: 7413980
    Abstract: One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink that is located over and contacts the first metal layer.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: August 19, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Honglin Guo, Dongmei Lei, Brian Goodlin, Joe McPherson