Patents by Inventor Honglin Guo
Honglin Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901462Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.Type: GrantFiled: February 5, 2022Date of Patent: February 13, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Honglin Guo, Zachary K Lee, Jingjing Chen
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Patent number: 11881462Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.Type: GrantFiled: September 28, 2020Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventor: Honglin Guo
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Publication number: 20230378005Abstract: A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Honglin Guo, Robert M. Higgins
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Publication number: 20230307557Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.Type: ApplicationFiled: February 5, 2022Publication date: September 28, 2023Inventors: Honglin Guo, Zachary K Lee, Jingjing Chen
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Publication number: 20230253407Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.Type: ApplicationFiled: February 5, 2022Publication date: August 10, 2023Inventors: Honglin Guo, Frank John Sweeney
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Publication number: 20230129461Abstract: An integrated circuit includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor is electrically connected to a first circuit node and has first and second capacitor plates separated by a first dielectric stack. The second isolation capacitor is electrically connected in series between the first isolation capacitor and a second circuit node, and includes third and fourth capacitor plates separated by a second dielectric stack different from the first dielectric stack.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Inventors: Honglin Guo, Thomas D. Bonifield
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Publication number: 20230129759Abstract: This description relates generally to semiconductor devices. A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Inventors: HONGLIN GUO, THOMAS DYER BONIFIELD
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Publication number: 20230036643Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Mahmud Halim CHOWDHURY, Amin SIJELMASSI, Murali KITTAPPA, Anindya PODDAR, Honglin GUO, Joe Adam GARCIA, John Paul TELLKAMP
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Patent number: 11424183Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: GrantFiled: August 17, 2020Date of Patent: August 23, 2022Assignee: Texas Instruments IncorporatedInventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
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Patent number: 11227852Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.Type: GrantFiled: April 21, 2020Date of Patent: January 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
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Patent number: 11069627Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.Type: GrantFiled: September 15, 2015Date of Patent: July 20, 2021Assignee: Texas Instruments IncorporatedInventors: Thomas D. Bonifield, Jeffrey A. West, Byron Williams, Honglin Guo
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Patent number: 10992293Abstract: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.Type: GrantFiled: September 20, 2018Date of Patent: April 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiong Li, William Toth, Honglin Guo, Danyang Zhu
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Publication number: 20210098394Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.Type: ApplicationFiled: September 28, 2020Publication date: April 1, 2021Inventor: Honglin Guo
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Publication number: 20200381358Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Qi-Zhong HONG, Honglin GUO, Benjamin James Timmer, Gregory Boyd SHINN
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Patent number: 10784193Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: GrantFiled: July 27, 2018Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
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Publication number: 20200251440Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
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Patent number: 10629562Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.Type: GrantFiled: July 2, 2018Date of Patent: April 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
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Publication number: 20200096574Abstract: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.Type: ApplicationFiled: September 20, 2018Publication date: March 26, 2020Inventors: Xiong LI, William TOTH, Honglin GUO, Danyang ZHU
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Publication number: 20200035598Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: ApplicationFiled: July 27, 2018Publication date: January 30, 2020Inventors: QI-ZHONG HONG, HONGLIN GUO, BENJAMIN JAMES TIMMER, GREGORY BOYD SHINN
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Publication number: 20190206828Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.Type: ApplicationFiled: July 2, 2018Publication date: July 4, 2019Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR