Abstract: A two-step process for manufacturing a deep trench in a semiconductor device that prevents shorts and leakages between neighboring capacitors due to over etching is disclosed. The process comprises conducting a first etching step to remove a portion of a substrate to form a trench with a first determined depth therein; conducting a thermal oxidation to form an oxide film on the sidewall of the trench; and conducting a second etching step to remove a portion of the substrate under the trench to form a deep trench with a second determined depth.

Abstract: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concavity. A second mask is formed on the surface of the prepared structure, a second etching process is then performed to remove the second mask on the concavity, and a third etching process is performed subsequently to extend the depth of the concavity into the substrate. To prepare a conductor with high aspect ratio in the substrate, the first mask and the second mask are preferably made of dielectric material or metal. In addition, to prepare a trench with high aspect ratio in a silicon substrate, the first mask and the second mask are preferably made of dielectric material.

Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.

Abstract: The invention is directed to an etching method. The etching method comprises steps of providing a material layer having a patterned hard mask layer formed thereon and then performing a first dry etching process by using the patterned hard mask layer as a mask, wherein a first power mode of the first dry etching process is a pulse mode and the first dry etching process is performed for a first process time. A second dry etching process is performed by using the patterned hard mask layer as a mask, wherein a second power mode of the second dry etching process is a continued wave mode and the second dry etching process is performed for a second process time, and the ratio of the first process time to the second process time is about 0.1˜2.0.

Abstract: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concave. A second mask is formed on the surface of the prepared structure, a second etching process is then performed to remove the second mask on the concave, and a third etching process is performed subsequently to extend the depth of the concave into the substrate. To prepare a conductor with high aspect ratio in the substrate, the first mask and the second mask are preferably made of dielectric material or metal. In addition, to prepare a trench with high aspect ratio in a silicon substrate, the first mask and the second mask are preferably made of dielectric material.

Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.

Abstract: The present invention relates to a method of reducing needle-like defects generated on a wafer rim in an etching process, wherein the etching process using both a photoresist material and hardmask material as a mask. After removing the photoresist material and the hardmask material, said method comprising the steps of: (i) depositing the photoresist material on the wafer again; (ii) performing wafer edge exposure (WEE) to form a ring of the wafer edge; and (iii) performing dry etching to the exposed ring of wafer edge to remove the needle-like defects generated on the wafer edge.

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract: A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF4 and N2H2 as the main reactive gas; and (c) performing a water-rinsing process.

Abstract: A post-cleaning method of a via etching process in the present invention has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; b) performing a dry cleaning process which uses CF4 as the main reactive gas and is operated by dual powers; and (c) performing a water-rinsing process.

Abstract: A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF4 and N2H2 as the main reactive gas; and (c) performing a water-rinsing process.

Abstract: A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; removing the photoresist layer in an asher using a combination of oxygen plasma and water vapor, the ratio of oxygen plasma and water vapor being less than one; and performing a wet strip on the metal interconnect structure.

Abstract: A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer layers.

Abstract: A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.