Abstract: A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller is provided with an internal memory in addition to an external memory for write buffering, and may manage a buffer in different modes according to the write workload of a host.

Abstract: A memory controller and a storage device including the same are provided. The memory controller is provided with an internal memory in addition to an external memory for write buffering. Accordingly, the frequency of accessing the external memory may be reduced.

Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.

Abstract: A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.

Abstract: A humidifying air purifier includes a body frame having an opened front and rear, a fan housing coupled to a rear end of the body frame and having a fan intake, a housing cover coupled to a rear end of the fan housing to accommodate an air blowing fan, and an air discharge port formed at an upper end of the fan housing and an upper end of the housing cover. A waterwheel motor is installed on a front surface of the fan housing and positioned outside the fan intake, a driving gear is coupled to the waterwheel motor, a door assembly is configured to be pushed into or drawn out from a front end of the body frame, a water tub is accommodated in a lower side of the door assembly, and a humidifying filter assembly is inserted into the water tub.

Abstract: A memory controller and a storage device including the same are provided. The memory controller groups pages in a memory block into page groups of different classes according to bit error rates, and allocates a page to be programmed according to a reliability requirement of a logical block address (LBA).

Abstract: A memory controller and a storage device including the same are provided. The memory controller groups pages in a memory block into page groups of different classes according to bit error rates, and allocates a page to be programmed according to a reliability requirement of a logical block address (LBA).

Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.

Abstract: A memory controller and a storage device including the same are provided. The memory controller generates a plurality of scrambled data by randomizing input data, counts the number of toggles per bit of each scrambled data, and writes one scrambled data with a smallest number of toggles in a non-volatile memory.

Abstract: An interior permanent magnet motor includes a stator provided with a plurality of slots and a rotor rotatably disposed inside the stator. A plurality of permanent magnets of the same polarity are disposed at equal intervals in a circumferential direction inside the rotor. A plurality of flux bathers are provided on left and right sides of one end of each of the plurality of permanent magnets adjacent to an outer circumferential surface of the rotor. A ratio of a number of slots of the stator to a number of magnetic poles of the rotor is 3:2 or 3:4. The number of permanent magnets provided in the rotor is ½ of the number of magnetic poles of the rotor.

Abstract: An embodiment of the present invention relates to a flow generating device comprising: a main body comprising a first suction part and a second suction part disposed at sides opposite to each other, a first inner discharge part through which air suctioned into the first suction part passes, a second inner discharge part through which air suctioned into the second suction part passes, and at least one outer discharge part through which air passing through the first inner discharge part and air passing through the second inner discharge part are discharged to the outside; a first fan disposed between the first suction part and the first inner discharge part; and a second fan disposed between the second suction part and the second inner discharge part.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.

Abstract: A memory controller and a storage device including the same are provided. The memory controller for performing a buffering operation of temporarily storing data to be written to a non-volatile memory and data to be read from the non-volatile memory in a buffer memory includes a buffer request queue configured to store a plurality of buffer write requests requesting data to be temporarily stored in the buffer memory and a plurality of buffer read requests requesting data stored in the buffer memory to be read, a buffer traffic monitor configured to calculate the total amount of requested data in real time by summing the lengths of data specified in the respective buffer write requests and the respective buffer read requests stored in the buffer request queue, and a buffer manager configured to control execution of the buffering operation by setting an execution ratio based on the total amount of requested data calculated in real time.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: Disclosed is a compressor including a housing, and a motor including a stator to be interference fitted into and fixed to an inner circumferential surface of the housing and a rotor rotatable inside the stator. The stator includes an annular back yoke disposed inside the housing, a plurality of teeth extending radially inward from the back yoke, and a coil wound on the plurality of teeth. The back yoke includes a deformation portion compressed and deformed by the housing while the stator is interference fitted into the inner circumferential surface of the housing, a contact portion which protrudes radially outward from the deformation portion and being in contact with the housing, and a cavity formed on a radial inner side of the deformation portion into which which the deformation portion is deformed.

Abstract: An embodiment of the present invention relates to a flow generating device comprising: a main body comprising a first suction part and a second suction part disposed at sides opposite to each other, a first inner discharge part through which air suctioned into the first suction part passes, a second inner discharge part through which air suctioned into the second suction part passes, and at least one outer discharge part through which air passing through the first inner discharge part and air passing through the second inner discharge part are discharged to the outside; a first fan disposed between the first suction part and the first inner discharge part; and a second fan disposed between the second suction part and the second inner discharge part.