Abstract: Upon determining that a first read operation on one memory cell of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to second word line, and a first pass voltage is applied to third word line. The second word line include one or more word lines adjacent to a selected word line, and the third word line include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the second word line in the first read operation. The second pass voltage is higher than the first pass voltage.

Abstract: Examples of the present application disclose a memory device, a memory system, and an operation method of a memory device. In the method, prior to ISPP programming of memory cells of selected memory cells, a first preprogram pulse is first applied to a selected word line to preprogram a first class of memory cells of the selected memory cells.

Abstract: Example memory devices, memory systems, and methods for reducing time of program operation in NAND flash memory are disclosed. One example method includes programming a first memory cell in a first memory cell string of a memory cell array by applying a first programming voltage to a first word line coupled to the first memory cell string from a first time to a second time. A second programming voltage higher than or equal to the first programming voltage is applied to the first word line from the second time to a third time to program a second memory cell in a second memory cell string of the memory cell array, where the first word line is coupled to the second memory cell string.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Abstract: Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

Abstract: A memory device includes a memory string, and a control logic coupled to the memory string. The control logic is configured to perform a first programming operation and a second programming operation on a selected memory cell of the memory string, after the first programming operation and before the second programming operation, apply a ground voltage to a first word line coupled to the selected memory cell, and apply a first voltage to a second word line coupled to an unselected memory cell of the memory string, wherein the first voltage is higher than the ground voltage.

Abstract: Disclosure includes systems, methods and devices to program a memory device, involving a first and a second programming operations on a memory cell of the memory device. In the first programming operation, the memory cell is programmed into an intermediate state. In the second programming operation, the memory cell is programmed from the intermediate state into a target state. The first programming operation includes providing a bias voltage to a bit line coupled to the memory cell and providing a programming voltage to a word line coupled to the memory cell. An amplitude of the bias voltage provided to the bit line depends on the intermediate state or the target state the memory cell to be programmed into. Accordingly, no verification operation need to be performed on the memory cell in the first programming operation.

Abstract: The disclosure provides a programming method of a memory, a memory and a memory system, which relate to the technical field of semiconductor chips. The programming method comprises: applying a program voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; and during a stage of applying the program voltage to the first word line, applying a turn-on voltage to a first select line and a second select line sequentially, wherein the first select line is coupled to a select transistor of the first memory cell slice, and the second select line is coupled to a select transistor of the second memory cell slice.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Abstract: The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Abstract: The present disclosure provides a method of operating a memory, a memory, a memory system and an electronic device. In an example, a method of operating a memory is provided. The memory includes multiple word lines, and each of the plurality of word lines is coupled to a plurality of memory cells. The method includes: performing a first programming operation on a plurality of memory cells coupled to a selected word line among the multiple word lines, the first programming operation including applying a one-pulse to the selected word line to program the multiple memory cells coupled to the selected word line into N programmed states; and performing a second programming operation on the selected word line to program the multiple memory cells coupled to the selected word line into N target programmed states, where N is a positive integer.

Abstract: A memory, a memory system and a method of operating the memory are disclosed, belonging to the field of storage technologies. When an erase operation is performed on various strings in the block of the memory, if there are a first string that has been erased and a second string that has not been erased among the strings, the selection line coupled to the first selection transistor of the first string is floated in advance before the selection line coupled to the first selection transistor of the second string is floated, to thereby reduce the erasing speed of the first string and prevent the first string from being over-erased during the erasing of the second string, which reduces the possibility of lateral spreading of memory cells in the subsequent first string after programming, and weakens the threshold voltage drift of the memory cells in the first string.

Abstract: A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Abstract: A memory device includes a memory cell array and peripheral circuits coupled to the memory cell array. The peripheral circuits are configured to perform twice program operations on one or more first memory cells in the memory cell array for storing cold data into the one or more first memory cells. The twice program operations include a first time program operation and a second time program operation. To perform the twice program operations, the peripheral circuits are configured to performing the first time program operation for successfully storing the cold data into the one or more first memory cells, and performing the second time program operation for improving retention characteristics of the cold data.

Abstract: A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.

Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Abstract: A plasma jet generator includes a base, a jet gun cavity, a blocking insulating medium, a porous air intake plate, a high-voltage port, a high-voltage electrode housing, and a jet gun tip. The base is detachably connected to a first end of the jet gun cavity. The blocking insulating medium is inserted in the base. The porous air intake plate is detachably mounted in the blocking insulating medium. The high-voltage electrode housing is detachably mounted in the porous air intake plate. The high-voltage port is disposed in the high-voltage electrode housing. The jet gun tip is detachably mounted at a second end of the jet gun cavity.