Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3, A1 to A3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: A method for preparing a shell-bionic ceramic tool and a shell-bionic ceramic tool, wherein the shell-bionic ceramic tool includes alternating stacks of ceramic powders with different components, pressing a ceramic green body using a cold briquetting method, carrying out pre-pressing once using a graphite indenter on a working surface thereof after each layer of the ceramic powder being loaded, and pressing a last layer using a graphite rod, and then pressing a whole ceramic green body with a certain pressure to promote a bonding of the layers of ceramic powder, which in turn gives a complex shape to an interface between the layers, increases a bonding area between the layers, and plays the role of hindering crack expansion, extending the crack expansion path, and improving the bonding strength of the interface; after then, hot-pressed sintering is used to densify the ceramic green body to obtain the shell-bionic ceramic tool.

Abstract: A hydrogel for cell-laden bioprinting, bioink, and a preparation method and an application thereof, relates to the technical field of biomedical polymer hydrogels. The hydrogel for cell-laden bioprinting is polymer gel formed by adding a cell-specific material into a matrix of alginate and gelatin and crosslinking and curing, wherein the cell-specific material is polypeptide selected according to different laden cells. The structures printed using the hydrogel may have the advantages such as adjustable mechanical properties, adjustable porosity, high biocompatibility, high printing accuracy, and high customizability, which may widely support the printing of human tissues and organs such as spinal cord, cartilage, and heart, and has good prospects for applications in tissue repair, organ transplantation and so on.

Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: The present disclosure relates to methods and devices for accessing a service device in a local area network. One example method includes sending a first request message to a first router, receiving a first feedback message sent by the first router, and accessing at least one service device by using a communication address of an electronic device in a second network. The first request message is used to request the communication address of the electronic device in the second network. The first feedback message is used to indicate the communication address of the electronic device in the second network.

Abstract: The present disclosure provides a magnetron sputtering apparatus, including a process chamber, a bias power supply assembly, and an excitation power supply assembly. The process chamber is provided with a base assembly and a bias guide assembly. A target is arranged at a top of the process chamber. The base assembly is arranged at a bottom of the process chamber and is configured to support a wafer carrier, drive the wafer carrier to move, and heat the wafer carrier. The bias guide assembly is arranged at the base assembly and configured to support the wafer carrier. The bias guide assembly is electrically in contact with the wafer carrier. The bias power supply assembly is electrically connected to the bias guide assembly and configured to apply a bias voltage to the wafer carrier through the bias guide assembly.

Abstract: An alumina-based ceramic tool material with low thermal expansion and a preparation process thereof, accordingly, the ceramic tool material may have both the high hardness of alumina ceramics after the hot pressing sintering, and reduces the thermal expansion coefficient of the overall ceramic material by adding the Sc2W3O12 as the negative thermal expansion phase, which improves the thermal shock resistance of ceramic tools in high-speed cutting engineering and meets the requirements of large temperature range during the machining of nickel-based superalloys. Moreover, the composite material does not use metal binder and has strong thermal stability even in the high-speed machining under extreme heat-force-chemistry coupling, so it has a high machining compatibility for nickel-based superalloys.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Abstract: The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon.

Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3, m and n are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I), wherein R1 and R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I) and pharmaceutically acceptable salts thereof. The compounds act as antagonists of the toll-like receptors TLR7, TLR8 and/or TLR9 and are thus useful in the treatment of systemic lupus erythematosus (SLE) and lupus nephritis.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 and n are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to compounds of formula (I), wherein R1, R2 and R3 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds as antagonist of TLR7 and/or TLR8 and/or TLR9 in the treatment of autoimmune diseases as well as auto-inflammation diseases.

Abstract: The present invention relates to compounds of formula (I), wherein R1 to R3 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.