Abstract: This Invention involves the smart photo frame in technical field. Specifically, it relates to a smart photo frame that supports sonic wave configuration free of unpacking for gift giving. The smart photo frame comprises hardware components and a photo frame design, and the hardware components comprise a microphone capable of receiving ultrasonic waves, a network module, a storage device, a display, a processor, audio output devices, power supply components, operation keys, and a touch screen. The design of the photo frame includes 7 steps, and the specific steps will be discussed in detail thereinafter. This Invention is of wireless convenience, high efficiency and reliability by sonic wave configuration. And the smart photo frame is of comprehensive function, optimized user experience, and it can protect data security and personal privacy, improve the testing and evaluation, and provide an excellent product experience.

Abstract: A GaN-based High Electron Mobility Transistor (HEMT) having a multi-threshold voltage, a preparation method, and an application therefor are provided. The HEMT structure includes a channel layer and a barrier layer; a Two-dimensional Electron Gas (2DEG) is formed between the channel layer and the barrier layer; the barrier layer is at least provided with a first source area, a second source area, a first gate area, a second gate area, a first drain area, and a second drain area; the first source area, the first gate area, and the first drain area cooperate with each other, so as to form a first HEMT unit; the second source area, the second gate area, and the second drain area cooperate with each other, so as to form a second HEMT unit. that the HEMT may well meet application requirements of high and low threshold logic circuits.

Abstract: The present disclosure relates to a composition capable of promoting hair growth, including a pulchinenoside active component of pulchinenoside B4 or pulchinenoside B5. The experiment results are showed that the composition of the present disclosure can promote hair growth in a hair removal area of mice, improve its growth speed and increase the number of hair follicles, and has non-toxic side effects, low cost and rapid curative effect. The present disclosure also discloses a drug capable of promoting hair growth, including a pulchinenoside active component of pulchinenoside B4 or pulchinenoside B5. The present disclosure also discloses pulchinenoside B4 or pulchinenoside B5 as an active component in preparation of the composition or drug capable of promoting hair growth.

Abstract: The present application discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises manufacturing a semiconductor material layer comprising two laminated semiconductor layers between which an etching transition layer is provided; and etching a part of one of semiconductor layers located in a selected region until etching is stopped after reaching or entering the etching transition layer, subjecting the part of the etching transition layer located in the selected region to thermal decomposition through thermal treatment to be completely removed, and realizing termination of thermal decomposition on another semiconductor layer, so as to precisely form a trench structure in the semiconductor material layer.

Abstract: The present disclosure relates to an application of anemoside B4 in preparation of drug for treatment or prevention of psoriasis. Anemoside B4 has therapeutic effect on 5% imiquimod-induced psoriatic lesions in mice. Its possible mechanism may be inhibiting inflammation reactions, regulating immune function and inhibiting angiogenesis, and the therapeutic effect may be realized by inhibiting the release of IL-12, IL-17, IL-6 and IL-1? in skin tissue. This study of the present disclosure laid a theoretical foundation for the subsequent development of anemoside B4 into an anti-psoriasis drug of traditional Chinese medicine.

Abstract: The present disclosure relates to an application of anemoside B4 in preparation of drug for treatment or prevention of psoriasis. Anemoside B4 has therapeutic effect on 5% imiquimod-induced psoriatic lesions in mice. Its possible mechanism may be inhibiting inflammation reactions, regulating immune function and inhibiting angiogenesis, and the therapeutic effect may be realized by inhibiting the release of IL-12, IL-17, IL-6 and IL-1? in skin tissue. This study of the present disclosure laid a theoretical foundation for the subsequent development of anemoside B4 into an anti-psoriasis drug of traditional Chinese medicine.

Abstract: Disclosed are a special robot with complex terrain adaptive function and a motion and operation method thereof. The special robot comprises a crawler chassis, a shock absorption suspension assembly, a suspension adaptive adjustment assembly and an electronic control assembly. The present disclosure achieves an adaptive angle adjustment on the left and right sides of the shock absorption suspension assembly, including the independent pitch angle and roller angle adjustment on the left and right sides of the shock absorption suspension assembly by the configuration of structures such as the suspension adaptive adjustment assembly and then achieves the adaptability of the robot on complex and tough pavement conditions by the combination with a sensor for pavement perception, which ensures walking performance and attachment ability of mechanisms, further improves the load-bearing performance of the crawler robot, ensures the safety, stability and adaptability of the mobile platform.

Abstract: A group III nitride enhancement-mode HEMT based on a composite barrier layer structure and a manufacturing method thereof are provided. The HEMT includes first and second semiconductors respectively serving as a channel layer and a barrier layer, a third semiconductor serving as a p-type layer, a source, a drain and a gate, wherein a recessed structure is formed in the region of the barrier layer corresponding to the gate, which is matched with the third semiconductor and the gate to form a p-type gate, and the second semiconductor includes first and second structure layers successively arranged on the first semiconductor; relative to the selected etching reagent, the first structure layer has higher etching resistance than the second structure layer.

Abstract: Disclosed are a special robot with complex terrain adaptive function and a motion and operation method thereof. The special robot comprises a crawler chassis, a shock absorption suspension assembly, a suspension adaptive adjustment assembly and an electronic control assembly. The present disclosure achieves an adaptive angle adjustment on the left and right sides of the shock absorption suspension assembly, including the independent pitch angle and roller angle adjustment on the left and right sides of the shock absorption suspension assembly by the configuration of structures such as the suspension adaptive adjustment assembly and then achieves the adaptability of the robot on complex and tough pavement conditions by the combination with a sensor for pavement perception, which ensures walking performance and attachment ability of mechanisms, further improves the load-bearing performance of the crawler robot, ensures the safety, stability and adaptability of the mobile platform.

Abstract: A data optimization method and an integral prestack depth migration method are provided, including acquiring a target matrix to be optimized; generating a first sequence according to the target matrix; rarefying the first sequence according to a preset grid density to obtain a value position of each element of a second sequence, and working out a value of each element of the second sequence on the basis of the principle of least squares; performing interpolation on the second sequence to obtain a third sequence; calculating a target matrix corresponding to the third sequence; calculating an error between the target matrix to be optimized and the target matrix corresponding to the third sequence; recording, when the error is less than the first error threshold, the target matrix corresponding to the above second sequence as an optimized target matrix of the target matrix to be optimized.

Abstract: The present application discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises manufacturing a semiconductor material layer comprising two laminated semiconductor layers between which an etching transition layer is provided; and etching a part of one of semiconductor layers located in a selected region until etching is stopped after reaching or entering the etching transition layer, subjecting the part of the etching transition layer located in the selected region to thermal decomposition through thermal treatment to be completely removed, and realizing termination of thermal decomposition on another semiconductor layer, so as to precisely form a trench structure in the semiconductor material layer.

Abstract: A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.

Abstract: The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.

Abstract: The present disclosure belongs to the field of display technology, and particularly relates to a test circuit, a display substrate, a test method of a display substrate and a display apparatus. The test circuit includes a signal generating device and a plurality of output channels that are mutually independent. Each output channel includes a signal line configured to transmit a test signal. The signal generating device is coupled to the plurality of output channels, and is configured to provide, to each of at least one of the plurality of output channels, the test signal corresponding to an impedance of the signal line in the output channel, and provide the test signal to the signal line in the output channel.

Abstract: A group III nitride enhancement-mode HEMT based on a composite barrier layer structure and a manufacturing method thereof are provided. The HEMT includes first and second semiconductors respectively serving as a channel layer and a barrier layer, a third semiconductor serving as a p-type layer, a source, a drain and a gate, wherein a recessed structure is formed in the region of the barrier layer corresponding to the gate, which is matched with the third semiconductor and the gate to form a p-type gate, and the second semiconductor includes first and second structure layers successively arranged on the first semiconductor; relative to the selected etching reagent, the first structure layer has higher etching resistance than the second structure layer.

Abstract: A data optimization method and an integral prestack depth migration method are provided, including acquiring a target matrix to be optimized; generating a first sequence according to the target matrix; rarefying the first sequence according to a preset grid density to obtain a value position of each element of a second sequence, and working out a value of each element of the second sequence on the basis of the principle of least squares; performing interpolation on the second sequence to obtain a third sequence; calculating a target matrix corresponding to the third sequence; calculating an error between the target matrix to be optimized and the target matrix corresponding to the third sequence; recording, when the error is less than the first error threshold, the target matrix corresponding to the above second sequence as an optimized target matrix of the target matrix to be optimized.

Abstract: The present application discloses a nitride semiconductor light-emitting device and a manufacture method thereof. The nitride semiconductor light-emitting device includes an epitaxial structure, wherein the epitaxial structure has a first face and a second face opposite to the first face, the first face is a (0001) nitrogen face and located at the n type side of the epitaxial structure, the second face is located at the p type side of the epitaxial structure, the n type side of the epitaxial structure is electrically contacted with an n type electrode, the p type side is electrically contacted with a p type electrode, and a ridge waveguide structure is formed on the first face.

Abstract: A set of measurement voltages having different voltage values are subsequently inputted to a measurement voltage input terminal of the pixel driving circuit, a light emitting state of a light emitting device under each measurement voltage is detected, and it is determined whether a storage capacitor in the pixel driving circuit is normal based on the light emitting state of the light emitting device.

Abstract: The present application discloses a nitride semiconductor light-emitting device and a manufacture method thereof. The nitride semiconductor light-emitting device includes an epitaxial structure, wherein the epitaxial structure has a first face and a second face opposite to the first face, the first face is a (0001) nitrogen face and located at the n type side of the epitaxial structure, the second face is located at the p type side of the epitaxial structure, the n type side of the epitaxial structure is electrically contacted with an n type electrode, the p type side is electrically contacted with a p type electrode, and a ridge waveguide structure is formed on the first face.

Abstract: A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.