Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable electrical traces on glass cores in integrated circuit packages that includes an integrated circuit (IC) package substrate comprising a glass core, a photo-imageable dielectric (PID) material on the glass core, and metal interconnects in openings in the PID material.

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate with a stress buffer dielectric between the contact and the bulk dielectric. The bulk dielectric typically covers an integrated circuit metal layer to provide electrical isolation of the circuitry. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The stress buffer dielectric has higher elongation and lower filler loading relative to the bulk dielectric, which makes the stress buffer more pliable. The stress buffer is disposed between the contact and the bulk dielectric to improve stress response, reducing the possibility of delamination of the contact from the bulk dielectric.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

Abstract: Semiconductor devices having hollow filler materials are disclosed. A disclosed example semiconductor device includes at least one of a substrate or an interposer, interconnects extending through the at least one of the substrate or the interposer, and a composite material integral with or covering at least a portion of the semiconductor device, the composite material including a polymer matrix with a hollow filler material having voids therein.

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.