Patents by Inventor Hongyu Yue

Hongyu Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9017933
    Abstract: A method for treating a dielectric film on a substrate and, in particular, a method for integrating a low-k dielectric film with subsequently formed metal interconnects is described. The method includes preparing a dielectric film on a substrate, wherein the dielectric film is a low-k dielectric film having a dielectric constant less than or equal to a value of about 4. Thereafter, the method further includes performing a preliminary curing process on the dielectric film, forming a pattern in the dielectric film using a lithographic process and an etching process, removing undesired residues from the substrate, and performing a final curing process on the dielectric film, wherein the final curing process includes irradiating the substrate with ultraviolet (UV) radiation.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: April 28, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Dorel I. Toma, Hongyu Yue
  • Patent number: 8916055
    Abstract: A processing method and apparatus uses at least one electric field applicator (34) biased to produce a spatial-temporal electric field to affect a processing medium (26), suspended nano-objects (28) or the substrate (30) in processing, interacting with the dipole properties of the medium (26) or particles to construct structure on the substrate (30). The apparatus may include a magnetic field, an acoustic field, an optical force, or other generation device. The processing may affect selective localized layers on the substrate (30) or may control orientation of particles in the layers, control movement of dielectrophoretic particles or media, or cause suspended particles of different properties to follow different paths in the processing medium (26). Depositing or modifying a layer on the substrate (30) may be carried out.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 23, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Jozef Brcka, Jacques Faguet, Eric M. Lee, Hongyu Yue
  • Patent number: 8895942
    Abstract: A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Jacques Faguet, Eric M. Lee, Dorel I. Toma, Hongyu Yue
  • Patent number: 8530247
    Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Douglas Reid, James David Bernstein, Hongyu Yue, Howie Hui Yang, Mark Boehm
  • Publication number: 20130217210
    Abstract: A processing method and apparatus uses at least one electric field applicator (34) biased to produce a spatial-temporal electric field to affect a processing medium (26), suspended nano-objects (28) or the substrate (30) in processing, interacting with the dipole properties of the medium (26) or particles to construct structure on the substrate (30). The apparatus may include a magnetic field, an acoustic field, an optical force, or other generation device. The processing may affect selective localized layers on the substrate (30) or may control orientation of particles in the layers, control movement of dielectrophoretic particles or media, or cause suspended particles of different properties to follow different paths in the processing medium (26). Depositing or modifying a layer on the substrate (30) may be carried out.
    Type: Application
    Filed: July 31, 2012
    Publication date: August 22, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jozef Brcka, Jacques Faguet, Eric M. Lee, Hongyu Yue
  • Publication number: 20120225568
    Abstract: An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Yusaku IZAWA, Junjun LIU, Hongyu YUE, Dorel TOMA
  • Patent number: 8242460
    Abstract: A process module for treating a dielectric film and, in particular, a process module for exposing, for example, a low dielectric constant (low-k) dielectric film to ultraviolet (UV) radiation is described. The process module includes a process chamber, a substrate holder coupled to the process chamber and configured to support a substrate, and a radiation source coupled to the process chamber and configured to expose the dielectric film to electromagnetic (EM) radiation. The radiation source includes a UV source, wherein the UV source has a UV lamp, and a reflector for directing reflected UV radiation from the UV lamp to the substrate. The reflector has a dichroic reflector, and a non-absorbing reflector disposed between the UV lamp and the substrate, and configured to reflect UV radiation from the UV lamp towards the dichroic reflector, wherein the non-absorbing reflector substantially prevents direct UV radiation from the UV lamp to the substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 14, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Hongyu Yue, Junjun Liu, Jacques Faguet, Dorel I. Toma
  • Patent number: 8048326
    Abstract: The present invention presents a plasma processing system for etching a layer on a substrate comprising a process chamber, a diagnostic system coupled to the process chamber and configured to measure at least one endpoint signal, and a controller coupled to the diagnostic system and configured to determine in-situ at least one of an etch rate and an etch rate uniformity of the etching from the endpoint signal. Furthermore, an in-situ method of determining an etch property for etching a layer on a substrate in a plasma processing system is presented comprising the steps: providing a thickness of the layer; etching the layer on the substrate; measuring at least one endpoint signal using a diagnostic system coupled to the plasma processing system, wherein the endpoint signal comprises an endpoint transition; and determining the etch rate from a ratio of the thickness to a difference between a time during the endpoint transition and a starting time of the etching.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: November 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hongyu Yue, Hieu A. Lam
  • Publication number: 20110233430
    Abstract: A process module for treating a dielectric film and, in particular, a process module for exposing, for example, a low dielectric constant (low-k) dielectric film to ultraviolet (UV) radiation is described. The process module includes a process chamber, a substrate holder coupled to the process chamber and configured to support a substrate, and a radiation source coupled to the process chamber and configured to expose the dielectric film to electromagnetic (EM) radiation. The radiation source includes a UV source, wherein the UV source has a UV lamp, and a reflector for directing reflected UV radiation from the UV lamp to the substrate. The reflector has a dichroic reflector, and a non-absorbing reflector disposed between the UV lamp and the substrate, and configured to reflect UV radiation from the UV lamp towards the dichroic reflector, wherein the non-absorbing reflector substantially prevents direct UV radiation from the UV lamp to the substrate.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hongyu YUE, Junjun LIU, Jacques FAGUET, Dorel I. TOMA
  • Publication number: 20110237080
    Abstract: A method for treating a dielectric film on a substrate and, in particular, a method for integrating a low-k dielectric film with subsequently formed metal interconnects is described. The method includes preparing a dielectric film on a substrate, wherein the dielectric film is a low-k dielectric film having a dielectric constant less than or equal to a value of about 4. Thereafter, the method further includes performing a preliminary curing process on the dielectric film, forming a pattern in the dielectric film using a lithographic process and an etching process, removing undesired residues from the substrate, and performing a final curing process on the dielectric film, wherein the final curing process includes irradiating the substrate with ultraviolet (UV) radiation.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun LIU, Dorel I. TOMA, Hongyu YUE
  • Publication number: 20110232677
    Abstract: A method and system for treating a substrate and, in particular, a method and system for cleaning a low dielectric constant (low-k) dielectric film to remove, among other things, undesired residue is described. The method includes irradiating a region on a substrate containing one or more layers or structures with infrared (IR) radiation and optionally ultraviolet (UV) radiation to remove material or undesired residues from the one or more layers or structures. Furthermore, the method may optionally include exposing at least a portion of the region to a gas or vapor jet emanating from a gas nozzle along a jet axis in a direction towards the substrate.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun LIU, Dorel I. TOMA, Hongyu YUE
  • Patent number: 7972483
    Abstract: A method for material processing utilizing a material processing system to perform a process. The method performs a process (510), measures a scan of data (520), and transforms the data scan (530) into a signature (540) including at least one spatial component. The scan of data (530) can include a process performance parameter such as an etch rate, an etch selectivity, a deposition rate, a film property, etc. The signature (540) can be stored (550), and compared with either a previously acquired signature or with an ideal signature (560). If at least one spatial component substantially deviates from the reference spatial component, then a process fault has potentially occurred. If the cumulative deviation of all spatial components or a select group of components substantially deviates from a reference set of spatial components, then a process fault has potentially occurred.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: July 5, 2011
    Assignee: Tokyo Electron Limited
    Inventors: John Donohue, Hongyu Yue
  • Patent number: 7844559
    Abstract: A method for constructing a process performance prediction model for a material processing system, the method including the steps of: recording tool data for a plurality of observations during a process in a process tool, the tool data comprises a plurality of tool data parameters; recording process performance data for the plurality of observations during the process in the process tool, the process performance data comprises one or more process performance parameters; performing a partial least squares analysis using the tool data and the process performance data; and computing correlation data from the partial least squares analysis.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Hieu A. Lam, Hongyu Yue, John Shriner
  • Patent number: 7713760
    Abstract: A method of monitoring a processing system for processing a substrate during the course of semiconductor manufacturing is described. The method comprises acquiring data from the processing system for a plurality of observations. It further comprises constructing a principal components analysis (PCA) model from the data, wherein a weighting factor is applied to at least one of the data variables in the acquired data. The PCA mode is utilized in conjunction with the acquisition of additional data, and at least one statistical quantity is determined for each additional observation. Upon setting a control limit for the processing system, the at least one statistical quantity is compared with the control limit for each additional observation. When, for example, the at least one statistical quantity exceeds the control limit, a fault for the processing system is detected.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: May 11, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Hongyu Yue, Hieu A. Lam
  • Publication number: 20100068897
    Abstract: A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun Liu, Jacques Faguet, Eric M. Lee, Dorel I. Toma, Hongyu Yue
  • Publication number: 20100065758
    Abstract: A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun Liu, Jacques Faguet, Eric M. Lee, Dorel I. Toma, Hongyu Yue
  • Publication number: 20100067886
    Abstract: A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun Liu, Jacques Faguet, Eric M. Lee, Dorel I. Toma, Hongyu Yue
  • Publication number: 20100065759
    Abstract: A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Junjun Liu, Jacques Faguet, Eric M. Lee, Dorel I. Toma, Hongyu Yue
  • Publication number: 20090311634
    Abstract: A method of patterning a thin film on a substrate is described. The method includes forming a sacrificial structure over the thin film, and forming a photo-resist layer over the sacrificial structure. The sacrificial structure has anti-reflective properties, comprises silicon and is capable of withstanding the photo-resist layer removal process and the stress induced during the spacer layer deposition. Thereafter, an image pattern is formed in one or both of the sacrificial structure or the photo-resist layer. A spacer layer is then conformally deposited over the pattern. The spacer layer is etched back to remove horizontal portions while substantially leaving vertical portions. The remaining photo-resist and/or sacrificial structure that is not overlaid with the etched-back spacer layer is removed leaving spacers that are utilized to transfer another pattern to the thin film.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hongyu Yue, Hieu A. Lam, Reiji Niino
  • Publication number: 20090170222
    Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.
    Type: Application
    Filed: November 25, 2008
    Publication date: July 2, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Brian Douglas Reid, James David Bernstein, Hongyu Yue, Howie Hui Yang, Mark Boehm