Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: A method and apparatus for performing a slicer and Viterbi decoding operations which are optimized for single-instruction/multiple-data type of parallel processor architectures. Some non-regular operations are eliminated and replaced with very regular repeatable tasks that can be efficiently parallelized. A first aspect of the invention provides a pre-slicer scheme where once eight input symbols for a Viterbi decoder are ascertained and their distances calculated, these distances are saved in an array. A second aspect of the invention provides a novel way of performing the path and branch metric calculations in parallel to minimize processor cycles. A third aspect of the invention provides a method to implement the Viterbi decoder without continually performing a trace back. Instead, the previous states along the maximum likelihood paths for each trellis state are stored. When the path with the shortest distance is later selected, determining the trace back state merely requires a memory access.

Abstract: A variable sample rate converter, adaptable to rational ratios, converts a plurality of data having a first sample rate to a plurality of data having a second sample rate. The variable sample rate converter is employed in data processing devices including, for example, color photo-copy machines, color facsimiles, color printers, black and white printers, digital cameras, and digital printers. A finite impulse response filter is employed to perform processing of the plurality of data. Any processing hardware capable of performing floating point processing may employ the variable sample rate converter. A ping-pong style buffer is employed to assist in transferring the plurality of data. The variable sample rate converter combines the two steps of up-sampling and down-sampling into a single step, thereby maximizing available processing resources.