Patents by Inventor Hoon Ahn

Hoon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND DEVICE FOR UPDATING LANGUAGE MODEL AND PERFORMING SPEECH RECOGNITION BASED ON LANGUAGE MODEL
    Publication number: 20170032779
    Abstract: A method of updating a grammar model used during speech recognition includes obtaining a corpus including at least one word, obtaining the at least one word from the corpus, splitting the at least one obtained word into at least one segment, generating a hint for recombining the at least one segment into the at least one word, and updating the grammar model by using at least one segment comprising the hint.
    Type: Application
    Filed: April 25, 2016
    Publication date: February 2, 2017
    Inventors: Dong-hoon AHN, Chi-youn PARK, Kyung-min LEE, Jae-won LEE
  • Encoding image data with quantizing and inverse-quantizing pixel values
    Patent number: 9560364
    Abstract: An image processing system and a method thereof is disclosed. A palette including an N number of index pixel values of a processing target image and corresponding index values is created. N is an integer equal to or smaller than 2. An image indexing process is performed on each processing target pixel. When a pixel value of the processing target pixel is a pixel value of one of the N number of index pixel values, a pixel data on a converted image corresponding to the processing target pixel is set as an index value on the palette corresponding to the pixel value of the processing target pixel. Otherwise, the pixel data on the converted image corresponding to the processing target pixel is set as an exceptional value, and the pixel value of the processing target pixel is stored in an exception buffer.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 31, 2017
    Assignees: FINGRAM CO., LTD., QURAM CO., LTD.
    Inventors: Young Cheul Wee, Young Hoon Ahn
  • USB port locking device
    Patent number: 9553408
    Abstract: Provided is a USB port locking device including: a blocking member having a blocking coupling part to block access of an external device; an external USB port part connected to the blocking member and to which an external USB connection port is insertively coupled; a signal connection part enabling signal transmission between a terminal inside the USB port of the electronic device and the external USB connecting port; a locking member selectively locked to the electronic device so that the blocking member is not forcedly removed; a stopping member selectively blocking an unauthorized external USB connecting port from being inserted into the external USB port part; and a lock member controlling a locking operation of the locking member and a blocking operation of the stopping member by interfering with the locking member and the stopping member when they are inserted into the blocking member.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 24, 2017
    Inventor: Chang Hoon Ahn
  • TRANSFER METHOD OF MATERIALS BY USING PETROLEUM JELLY
    Publication number: 20170001424
    Abstract: A method of transferring materials by using petroleum jelly is provided. An example of the method involves forming a material on a first substrate, forming a transfer support made from petroleum jelly on the material, removing the first substrate, stacking the material and the petroleum jelly transfer support after removing the first substrate on a second substrate, and removing the petroleum jelly transfer support.
    Type: Application
    Filed: January 8, 2016
    Publication date: January 5, 2017
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Soo-Min KIM, Joo-Song LEE, Dong-Ick SON, Seok-Hoon AHN, Myung-Jong KIM, Se-Gyu JANG, Hui-Su KIM
  • WIRING STRUCTURE AND METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE
    Publication number: 20160379891
    Abstract: In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 29, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: JIN-HYEUNG PARK, Yeon-Joo Kim, In-Hwan Kim, Jun-Jung Kim, Kyoung-Pil Park, Jeong-Hoon Ahn, Sang-Chul Lee, Joon-Nyung Lee, Hyo-Seon Lee
  • SEMICONDUCTOR DEVICES
    Publication number: 20160372415
    Abstract: A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.
    Type: Application
    Filed: February 4, 2016
    Publication date: December 22, 2016
    Inventors: Yong-Kong SIEW, Sang-Hoon AHN
  • Method of creating compound file and data storage device having the compound file
    Patent number: 9514392
    Abstract: A method for creating a compound file where additional data is inserted into an image file and a data storage device having the compound file recorded therein is provided. The method includes receiving, by a compound file creating apparatus, the image file and the additional data, and creating, by the compound file creating apparatus, the compound file by using the received image file and the additional data, wherein the compound file comprises an image file header corresponding to the image file, image data corresponding to the image file, and a marker recorded in a tail of the compound file and indicating that the compound file is an image file having the additional data inserted therein.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Cheul Wee, Young-Hoon Ahn
  • HIGH SPEED ACTUATOR INCLUDING ACTIVE STIFFNESS CONTROLLER AND METHOD OF DRIVING THE SAME
    Publication number: 20160352259
    Abstract: Disclosed is a high speed actuator. The high speed actuator includes an actuation part configured to cause deformation such as bending or twisting and an active stiffness controller on a surface of the actuation part or in the actuation part configured to control in real time a stiffness (e.g., of the actuator) according to an external signal. The active stiffness controller may control a stiffness of the high speed actuator in order for the actuator to be actuated at a high speed. Moreover, since the stiffness of the actuator is controlled in real time, a speed of the actuator may be controlled in real time.
    Type: Application
    Filed: May 25, 2016
    Publication date: December 1, 2016
    Applicant: SNU R&DB Foundation
    Inventors: Sung Hoon AHN, Sung Hyuk SONG
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20160343708
    Abstract: A semiconductor device may include a substrate, a plurality of first contact plugs, a first via and a power rail. The substrate may include first and second cell regions and a power rail region. The first and second cell regions may be disposed in a second direction, and the power rail region may be disposed between the first and second regions. The plurality of first contact plugs may be formed on the power rail region of the substrate, and may be spaced apart from each other by a first distance in a first direction crossing the second direction. The first via may commonly contact top surfaces of the first contact plugs. The power rail may be formed on the first via. The power rail may provide a voltage for the first and second cell regions through the first via and the first contact plugs.
    Type: Application
    Filed: February 19, 2016
    Publication date: November 24, 2016
    Inventors: Jungil PARK, Jeong-Hoon AHN, Junjung KIM, Chul-Yong PARK
  • CURVED TRANSPARENT SUBSTRATE, CURVED DISPLAY PANEL INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160342010
    Abstract: A curved transparent substrate includes an alkali-free base layer having a curved shape and a compression applying layer compression applying layer which is disposed on a surface of the alkali-free base layer and applies a compression to the alkali-free base layer where an alkali ion content of the compression applying layer is greater than an alkali ion content of the alkali-free base layer.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Inventors: Seung KIM, Seung-Ho KIM, Cheol-Min PARK, Sang-Hoon AHN, Eun-Kyung YEON, Hoi-Kwan LEE, In-Sun HWANG
  • WIRING STRUCTURES AND SEMICONDUCTOR DEVICES
    Publication number: 20160343660
    Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.
    Type: Application
    Filed: March 17, 2016
    Publication date: November 24, 2016
    Inventors: Jun-Jung KIM, Young-Bae KIM, Jong-Sam KIM, Jin-Hyeung PARK, Jeong-Hoon AHN, Hyeok-Sang OH, Kyoung-Woo LEE, Hyo-Seon LEE, Suk-Hee JANG
  • METHODS OF FORMING WIRING STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    Publication number: 20160329242
    Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.
    Type: Application
    Filed: February 19, 2016
    Publication date: November 10, 2016
    Inventors: Thomas OSZINDA, Tae-Jin YIM, Sang-Hoon AHN, Nae-In LEE
  • METHOD AND SYSTEM FOR IMAGE COMPRESSION USING IMAGE BLOCK CHARACTERISTICS
    Publication number: 20160316204
    Abstract: Method and system for adaptive image compression using block characteristics are provided. For adaptive image compression, blocks in an image are quantized and compressed using a quantization table that was used in quantization of the blocks. An image compression system checks a block-characteristics quantization table corresponding to a specific block in the image to be compressed in order to quantize the specific block, and performs calculation using a value of a first element of the quantization table corresponding to a specific element of the specific block and a value of a second element of the checked block-characteristics quantization table corresponding to the specific element in order to quantize the specific element.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: Young Cheul Wee, Young Hoon Ahn, Moo Jae Lee
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20160307842
    Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.
    Type: Application
    Filed: January 26, 2016
    Publication date: October 20, 2016
    Inventors: Jong-Min BAEK, Sang-Hoon AHN, Woo-Kyung YOU, Byung-Hee KIM, Young-Ju PARK, Nae-in LEE, Kyung-Min CHUNG
  • SEMICONDUCTOR DEVICES
    Publication number: 20160300792
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 13, 2016
    Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20160293552
    Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.
    Type: Application
    Filed: February 19, 2016
    Publication date: October 6, 2016
    Inventors: Tae-Jin YIM, Sang-Hoon AHN, Thomas OSZINDA, Jong-Min BAEK, Byung Hee KIM, Nae-In LEE, Kee-Young JUN
  • USB PORT LOCKING DEVICE
    Publication number: 20160294118
    Abstract: Provided is a USB port locking device including: a blocking member having a blocking coupling part to block access of an external device; an external USB port part connected to the blocking member and to which an external USB connection port is insertively coupled; a signal connection part enabling signal transmission between a terminal inside the USB port of the electronic device and the external USB connecting port; a locking member selectively locked to the electronic device so that the blocking member is not forcedly removed; a stopping member selectively blocking an unauthorized external USB connecting port from being inserted into the external USB port part; and a lock member controlling a locking operation of the locking member and a blocking operation of the stopping member by interfering with the locking member and the stopping member when they are inserted into the blocking member.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Inventor: Chang Hoon Ahn
  • Package module of battery protection circuit
    Patent number: 9450428
    Abstract: Disclosed is a package module of a battery protection circuit. The package module comprises: a first internal connection terminal area and a second internal connection terminal area, and in which first and second internal connection terminals connected to a battery can provided with a bare cell are respectively disposed; an external connection terminal area, in which a plurality of external connection terminals are disposed; and a protection circuit area comprising a device area in which a plurality of passive devices forming the battery protection circuit are disposed and a chip area, which is adjacent to the device area, and in which a protection IC and a dual FET chip forming the battery protection circuit are disposed, are disposed between the external connection terminal area and the second internal connection terminal area.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 20, 2016
    Assignee: ITM SEMICONDUCTOR CO., LTD.
    Inventors: Hyeok-Hwi Na, Young-Seok Kim, Sang-Hoon Ahn, Sung-Beum Park, Seung-Wook Park, Hyun-Mok Cho, Sun-Bok Park, Jae-Goo Park, Ho-Suk Hwang
  • LAN PORT LOCK DEVICE
    Publication number: 20160268734
    Abstract: Disclosed is a LAN port lock device for selectively locking a LAN port connector, having a resilient hook that is locked and coupled inside a LAN port of an electronic device when inserted into the LAN port, so as not to be separated when in the state coupled to the LAN port.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventor: Chang Hoon Ahn
  • SEMICONDUCTOR DEVICES INCLUDING SEALING REGIONS AND DECOUPLING CAPACITOR REGIONS
    Publication number: 20160240475
    Abstract: Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 18, 2016
    Inventors: Chul-yong PARK, Jeong-hoon AHN