Patents by Inventor Hoon Cha

Hoon Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250148362
    Abstract: Disclosed herein is an apparatus and method for managing a giant model. The apparatus includes memory in which at least one program is recorded and a processor for executing the program. The program may perform lightweighting a first model into a second model in consideration of hardware resources, generating partitioning information of the first model based on a result of analysis of the second model, and performing training or inference for the first model based on the generated partitioning information.
    Type: Application
    Filed: May 30, 2024
    Publication date: May 8, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Myung-Hoon CHA, Ki-Dong KANG, Hong-Yeon KIM, Baik-Song AN
  • Publication number: 20250122254
    Abstract: Provided are recombinant fusion proteins comprising an interleukin-18-binding protein and an antigen binding fragment against serum albumin and uses thereof. The recombinant fusion proteins have an improved administration cycle due to an increase in the half-life in the body. Further, the recombinant fusion proteins have low immunogenicity and do not cause side effects in vivo, and therefore, can be effectively used for the treatment of various cancers and immune diseases and conditions.
    Type: Application
    Filed: September 24, 2024
    Publication date: April 17, 2025
    Inventor: Sang Hoon Cha
  • Patent number: 12276566
    Abstract: Disclosed are an equipment malfunction diagnosis apparatus using a sound spectrogram image, and a method therefor. In other words, the present invention collects sound data through a sensor unit provided at one side of equipment, converts the collected sound data into a spectrogram image, and determines malfunction of the equipment and classifies a cause of the malfunction by performing machine learning using the spectrogram image as an input value, thereby quickly and accurately identifying the cause of the malfunction when it is identified that there is the malfunction in the equipment, and providing a counterplan in response thereto.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: April 15, 2025
    Assignee: WI.PLAT CO., LTD.
    Inventor: Sang Hoon Cha
  • Patent number: 12272428
    Abstract: A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 8, 2025
    Assignee: SK hynix Inc.
    Inventors: Se Ra Jeong, Kyung Hoon Kim, Ji Hwan Park, Ha Jun Jeong, Jae Hoon Cha
  • Patent number: 12210425
    Abstract: Disclosed herein are an apparatus and method for page allocation in a many-to-one virtualization environment. The method may include determining whether a page fault interrupt is caused by page initialization for page allocation, sending an ownership change message to a node having ownership of the corresponding page when the page fault interrupt is determined to be caused by page initialization, and initializing the corresponding page upon receiving an ownership-change-processing-complete message.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: January 28, 2025
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang-Min Lee, Hong-Yeon Kim, Baik-Song An, Myung-Hoon Cha
  • Publication number: 20240420754
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
  • Patent number: 12153811
    Abstract: Disclosed herein are an apparatus and method for processing fast persistent writing to nonvolatile memory. A method for processing fast persistent writing to a nonvolatile memory includes writing log data from a last storage position in a data block created in a certain size, reflecting the entire data block in a storage medium, increasing the last storage position by a size of the written log data, and reflecting the entire data block in a storage medium, wherein the data block is linearly linked to an additional data block in a creation order, and wherein the data block includes a log data storage region, information about a last storage position where the log data is stored in the log data storage region, and information about a linked next data block.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: November 26, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang-Min Lee, Hong-Yeon Kim, Baik-Song An, Myung-Hoon Cha
  • Publication number: 20240354019
    Abstract: When it is determined that a first super memory block among a plurality of super memory blocks satisfies an exchange condition, the storage device may exchange a first memory unit in the first super memory block with a second memory unit included in a second super memory block among the plurality of super memory blocks. In this case, the first memory unit is a bad memory unit and the second memory unit is a normal memory unit.
    Type: Application
    Filed: September 8, 2023
    Publication date: October 24, 2024
    Inventors: Jae Il LEE, Dong Hwan KOO, Duck Joo LEE, Joon Ho LEE, Young Hoon CHA
  • Publication number: 20240337561
    Abstract: Disclosed are an equipment malfunction diagnosis apparatus using a sound spectrogram image, and a method therefor. In other words, the present invention collects sound data through a sensor unit provided at one side of equipment, converts the collected sound data into a spectrogram image, and determines malfunction of the equipment and classifies a cause of the malfunction by performing machine learning using the spectrogram image as an input value, thereby quickly and accurately identifying the cause of the malfunction when it is identified that there is the malfunction in the equipment, and providing a counterplan in response thereto.
    Type: Application
    Filed: August 16, 2022
    Publication date: October 10, 2024
    Applicant: WI.PLAT CO., LTD.
    Inventor: Sang Hoon CHA
  • Patent number: 12106794
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: October 1, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Patent number: 12100602
    Abstract: A wet etching apparatus includes a process bath having an internal space configured to receive an etchant and having a support unit, on which a wafer is disposed to be in contact with the etchant. A laser unit is disposed above the process bath and is configured to direct a laser beam to the wafer and to heat the wafer thereby. An etchant supply unit is configured to supply the etchant to the internal space of the process bath.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: September 24, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Woo Lee, Yong Jun Choi, Seok Hoon Kim, Seung Min Shin, Ji Hoon Cha
  • Publication number: 20240264201
    Abstract: A pogo pin whose elastic force can be adjusted according to a contacting direction is disclosed. According to an aspect of the present invention, provided is a pogo pin with adjustable elastic force, including: a housing; plunger pins mounted on ends of the housing to directly contact a measurement object; and a spring installed inside the housing to provide elastic force so that the plunger pin contacts the measurement object, wherein a local fixing part protruding inward is formed on one side of the housing so that a first position of the spring can be pressed and fixed.
    Type: Application
    Filed: February 7, 2024
    Publication date: August 8, 2024
    Applicant: OKINS ELECTRONICS CO., LTD
    Inventors: Jin Kook JUN, Sang Hoon CHA
  • Publication number: 20240257891
    Abstract: A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.
    Type: Application
    Filed: September 1, 2023
    Publication date: August 1, 2024
    Applicant: SK hynix Inc.
    Inventors: Ji Hwan PARK, Kyung Hoon KIM, Se Ra JEONG, Ha Jun JEONG, Jae Hoon CHA
  • Patent number: 12042828
    Abstract: A wafer cleaning apparatus is provided. The wafer cleaning apparatus includes comprising a chamber configured to be loaded with a wafer, a nozzle on the wafer and configured to provide liquid chemicals on an upper surface of the wafer, a housing under the wafer, a laser module configured to irradiate laser on the wafer, a transparent window disposed between the wafer and the laser module, and a controller configured to control on/off of the laser module, wherein the controller is configured to control repetition of turning the laser module on and off, and retain temperature of the wafer within a temperature range, and a ratio of time when the laser module is on in one cycle including on/off of the laser module is 30% to 50%.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: July 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Min Shin, Hun Jae Jang, Seok Hoon Kim, Young-Hoo Kim, In Gi Kim, Tae-Hong Kim, Kun Tack Lee, Ji Hoon Cha, Yong Jun Choi
  • Patent number: 12033686
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: July 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Publication number: 20240218297
    Abstract: A semiconductor cleaning composition includes: a hydrophobic polymer, an organic acid; and a solvent, wherein the hydrophobic polymer includes a first allotrope and a second allotrope, wherein the first allotrope is nonpolar, wherein the second allotrope is polar, and wherein the second allotrope is about 5% to about 20% of the hydrophobic polymer.
    Type: Application
    Filed: September 11, 2023
    Publication date: July 4, 2024
    Applicant: Postech Research and Business Development Foundation
    Inventors: DAESUNG CHUNG, HAYOUNG JEON, JI HOON CHA, MINGYU JAE, KYUNGHYUN KIM, SUNGHOON YOO
  • Publication number: 20240176756
    Abstract: Disclosed herein is a method for distributed training of an AI model in a channel-sharing network environment. The method includes determining whether data parallel processing is applied, calculating a computation time and a communication time when input data is evenly distributed across multiple computation devices, and unevenly distributing the input data across the multiple computation devices based on the computation time and the communication time.
    Type: Application
    Filed: June 30, 2023
    Publication date: May 30, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ki-Dong KANG, Hong-Yeon KIM, Baik-Song AN, Myung-Hoon CHA
  • Publication number: 20240176759
    Abstract: Disclosed herein are a method for machine-learning parallelization using host CPUs of a multi-socket structure and an apparatus therefor. The method, performed by the apparatus for machine-learning parallelization using host CPUs of a multi-socket structure, includes a compile phase in which a learning model is split at a layer level for respective pipeline stages and allocated to Non-Uniform Memory Access (NUMA) nodes for respective CPU sockets and a runtime phase in which parameters required for learning are initialized and multiple threads generated in consideration of a policy of each parallelism algorithm are executed by being allocated to respective cores included in the NUMA node.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Baik-Song AN, Ki-Dong KANG, Hong-Yeon KIM, Myung-Hoon CHA
  • Publication number: 20240153792
    Abstract: An apparatus and method for processing a substrate can reduce the concentration of process by-products in a chemical solution.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Applicants: SEMES CO., LTD., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Jung KIM, Jin Ah HAN, Hee Hwan KIM, Yong Hoon HONG, Kyoung Suk KIM, Jong Hyeok PARK, Jin Hyung PARK, Dae Hyuk CHUNG, Ji Hoon CHA
  • Publication number: 20240147579
    Abstract: A cooking system is disclosed. The cooking system includes a microwave and a display device. The microwave is configured to in response to a received user command, generate a first image by photographing a cooktop located below the microwave through a first camera or generate a second image by photographing an inside of the microwave through a second camera. The microwave is also configured to transmit at least one of the first image and the second image to the display device. The display device is configured to receive the at least one of a first image and the second image from the microwave and display the received at least one image.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Jae-hoon CHA, Hyeong-jin JANG, Dong-hyun SOHN