Patents by Inventor Hoon Seok

Hoon Seok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145345
    Abstract: A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.
    Type: Application
    Filed: June 13, 2023
    Publication date: May 2, 2024
    Inventors: Yeonggil KIM, Hoon Seok SEO, Yungbae KIM, Wookyung YOU
  • Patent number: 11970394
    Abstract: Provided is a method of synthesizing apatite powder by emitting a laser beam to a surface of a substrate immersed in a precursor solution. The method is including immersing a substrate in an apatite-forming precursor solution, emitting a laser beam to a region on a surface of the substrate immersed in the precursor solution, and obtaining apatite powder generated in the precursor solution.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 30, 2024
    Assignee: Korea Institute of Science and Technology
    Inventors: Hojeong Jeon, Seung Hoon Um, Yu Chan Kim, Hyung-Seop Han, Myoung-Ryul Ok, Hyunseon Seo, Hyun Kwang Seok
  • Publication number: 20240118809
    Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.
    Type: Application
    Filed: February 9, 2023
    Publication date: April 11, 2024
    Inventor: Ji Hoon SEOK
  • Patent number: 11944238
    Abstract: A blender includes a container body in which food is accommodated, a main body to support the container body, and an air guide provided in the main body to guide discharging of air flowing through a motor assembly to below the main body.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: April 2, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Jun Ho Seok, Jong Ho Lee, Jeong Hoon Jeong, Young Soo Kim
  • Publication number: 20240087956
    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
  • Publication number: 20240045806
    Abstract: A storage device includes: a nonvolatile memory device; a volatile memory device including: a map data storage for temporarily storing a part of map data representing a relationship between a logical address of data, provided from a host device, and a physical address corresponding to a position in the nonvolatile memory device in which the data is stored; and a prefetch data storage for storing, as prefetch data, map data about at least two logical addresses prefetched from the host device; and a memory controller for controlling the nonvolatile memory device and the volatile memory device to process a multi-chunk read command as a read request for the at least two logical addresses received from the host device by using the prefetch data, and maintain the prefetch data in the prefetch data storage.
    Type: Application
    Filed: December 6, 2022
    Publication date: February 8, 2024
    Inventor: Ji Hoon SEOK
  • Publication number: 20240039036
    Abstract: A flexible self-supporting solid electrolyte membrane, an all-solid-state battery including the membrane, and a manufacturing method thereof are disclosed. The solid electrolyte membrane may include: a substrate including pores therein; and a solid electrolyte layer disposed on at least one surface of the substrate and including a solid electrolyte and a cured compound. At least a portion of the solid electrolyte layer may penetrate into the pores of the substrate to form a conduction path of lithium ions in a thickness direction of the substrate.
    Type: Application
    Filed: December 21, 2022
    Publication date: February 1, 2024
    Inventors: Hoon Seok, Yeong Jun Cheon, Hong Seok Min, Sang Young Lee, Kyeong Seok Oh, Yong Hyeok Lee
  • Patent number: 11876017
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
  • Patent number: 11823952
    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woojin Lee, Hoon Seok Seo, Sanghoon Ahn, Kyu-Hee Han
  • Publication number: 20230155446
    Abstract: Disclosed is a direct slot cooling system for motors, including a stator configured to expand an inner slot space of a stator core where a coil is wound to form a cooling slot through which a cooling fluid passes; a rotor coupled to a center of the stator to rotate; and a housing coupled to left and right sides of the stator to form a cooling jacket in watertight communication with a cooling slot so that a cooling fluid circulates in the cooling jacket.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 18, 2023
    Applicant: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Hong Soon CHOI, II Seouk PARK, Chang Hoon SEOK, Jun Beom PARK, Gui Hwan KIM, Jong Hui LEE, Jong Hyeon SON
  • Publication number: 20230121481
    Abstract: Disclosed are a hybrid solid electrolyte sheet and a method of manufacturing the same. The hybrid solid electrolyte sheet includes a hybrid solid electrolyte layer including a gel polymer electrolyte, thereby securing flexibility and alleviating brittleness. In addition, the hybrid solid electrolyte sheet includes a porous polymer film having a plurality of pores, thus minimizing the content of the acrylate monomer in the pores thereof and providing advantages of maintaining the continuity of the solid electrolyte while minimizing a decrease in ionic conductivity.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 20, 2023
    Inventors: Soon Chul Byun, Sang Mo Kim, Yong Seok Choi, Jae Min Lim, Hoon Seok, Sang Young Lee, Yong Hyeok Lee, Yi Su Jeong
  • Publication number: 20230114920
    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
  • Patent number: 11600569
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 11569128
    Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woojin Lee, Hoon Seok Seo, Sanghoon Ahn, Kyu-Hee Han
  • Publication number: 20220394936
    Abstract: The present disclosure relates a plant cultivation apparatus and a water supply control method thereof. The plant cultivation apparatus may perform water supply, lighting, dehumidification and the like to cultivate a plant according to a cultivation condition corresponding to a cultivation stage and a type of the plant provided in a cultivation room.
    Type: Application
    Filed: August 13, 2020
    Publication date: December 15, 2022
    Inventors: Hoon Seok CHOI, Tae Yang LEE
  • Patent number: 11526296
    Abstract: An operation method of a controller for controlling a memory device includes: queuing an identifier of a logical address region associated with a read request from a host in a most recently used (MRU) entry of an internal logical address region queue; increasing a weighted value for a read count of the logical address region by a first value according to whether the identifier of the logical address region has been queued in the logical address region queue before being queued in the MRU entry; adding the weighted value to the read count of the logical address region; providing the host with a map segment corresponding to the logical address region according to a threshold of the read count; and controlling a read operation of the memory device based on a physical address according to whether the read request includes the physical address.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Ho Ryong You, Su Hwan Kim, Seung Hun Kim, Ji Hoon Seok, Young Bin Song, Dong Sun Shin, Jae Yeon Jang
  • Patent number: 11494307
    Abstract: A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Seok
  • Patent number: 11487660
    Abstract: A storage device communicates with a host including a host memory. The storage device includes a semiconductor memory device and a device memory. The semiconductor memory device includes a plurality of non-volatile memory cells. The device memory stores validity information of host performance booster (HPB) sub-regions included in each of HPB regions cached in the host memory. The storage device determines to deactivate at least one HPB region among the HPB regions cached in the host memory based on the validity information included in the device memory, and transfers a message recommending to deactivate the determined HPB region to the host.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Seok
  • Publication number: 20220302425
    Abstract: Disclosed are a method and an apparatus of manufacturing an anode for an all-solid-state battery by using an electric field. The manufacturing method includes: preparing a first coating member and a second coating member spaced apart from the first coating member by a predetermined distance; preparing a coating slurry, the coating slurry including a carbon material and a metal alloyable with lithium; feeding the coating slurry to the first coating member; feeding a current collector between the first coating member and the second coating member; and coating the coating slurry on the current collector by using an electric field generated between the first coating member and the second coating member by applying voltages to the first coating member and the second coating member.
    Type: Application
    Filed: November 9, 2021
    Publication date: September 22, 2022
    Inventors: Yeong Jun Cheon, Hoon Seok
  • Publication number: 20220302493
    Abstract: A pouch-type all-solid-state battery having a reference electrode and a method of manufacturing the same, includes: a unit cell including an anode portion, a cathode portion, and a solid electrolyte portion having a sheet shape and located between the anode portion and the cathode portion; and an external member including a space for accommodating the unit cell therein, wherein the solid electrolyte portion includes: an electrode accommodating portion in which the anode portion and the cathode portion are accommodated; and an extension portion having a predetermined area extending from a side surface of the electrode accommodating portion, wherein a reference electrode portion is positioned on one surface of the extension portion.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 22, 2022
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Yong Guk Gwon, Hoon Seok, Min Sun Kim, Yong Seok Choi, Ju Min Kim