Abstract: Provided an electrode for secondary batteries, the electrode including: a substrate; and a plurality of active material layers arranged on the substrate and each including an active material, wherein at least one of the plurality of active material layers includes a binder, and a content of the binder is about 1.0 part by weight to about 1.7 parts by weight based on 100 parts by weight of a total weight of the plurality of active material layers.

Abstract: A plant cultivation apparatus and a method for controlling water supply in the plant cultivation apparatus are provided. The plant cultivation apparatus may supply feed water to a bed according to whether or not the feed water supplied to the bed to cultivate plants remains to prevent the feed water from being supplied more than necessary.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: Provided an electrode for secondary batteries, the electrode including: a substrate; and a plurality of active material layers arranged on the substrate and each including an active material, wherein at least one of the plurality of active material layers includes a binder, and a content of the binder is about 1.0 part by weight to about 1.7 parts by weight based on 100 parts by weight of a total weight of the plurality of active material layers.

Abstract: An embodiment method of manufacturing an all-solid-state battery includes forming a first electrode member by forming first active material layers on both surfaces of a first current collector, pressing the first electrode member to form a pressed first electrode member, forming a second electrode member by forming second active material layers on both surfaces of a second current collector and forming solid electrolyte layers on the second active material layers, pressing the second electrode member to form a pressed second electrode member, forming a laminated body by layering the pressed first electrode member and the pressed second electrode member, and pressing the laminated body by passing the laminated body between a pair of rollers to form a pressed laminated body.

Abstract: The present disclosure relates to a binder solution having lithium ion conductivity for an all-solid-state battery and an electrode slurry including the same. Specifically, the binder solution includes a first binder having high binding force, a second binder having higher lithium ion conductivity than that of the first binder, a lithium salt, and an organic solvent that dissolves the lithium salt.

Abstract: An embodiment method of manufacturing an all-solid-state battery includes forming a first electrode member by forming first active material layers on both surfaces of a first current collector, pressing the first electrode member to form a pressed first electrode member, forming a second electrode member by forming second active material layers on both surfaces of a second current collector and forming solid electrolyte layers on the second active material layers, pressing the second electrode member to form a pressed second electrode member, forming a laminated body by layering the pressed first electrode member and the pressed second electrode member, and pressing the laminated body by passing the laminated body between a pair of rollers to form a pressed laminated body.

Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.

Abstract: A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: A storage device includes: a nonvolatile memory device; a volatile memory device including: a map data storage for temporarily storing a part of map data representing a relationship between a logical address of data, provided from a host device, and a physical address corresponding to a position in the nonvolatile memory device in which the data is stored; and a prefetch data storage for storing, as prefetch data, map data about at least two logical addresses prefetched from the host device; and a memory controller for controlling the nonvolatile memory device and the volatile memory device to process a multi-chunk read command as a read request for the at least two logical addresses received from the host device by using the prefetch data, and maintain the prefetch data in the prefetch data storage.

Abstract: A flexible self-supporting solid electrolyte membrane, an all-solid-state battery including the membrane, and a manufacturing method thereof are disclosed. The solid electrolyte membrane may include: a substrate including pores therein; and a solid electrolyte layer disposed on at least one surface of the substrate and including a solid electrolyte and a cured compound. At least a portion of the solid electrolyte layer may penetrate into the pores of the substrate to form a conduction path of lithium ions in a thickness direction of the substrate.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: Disclosed is a direct slot cooling system for motors, including a stator configured to expand an inner slot space of a stator core where a coil is wound to form a cooling slot through which a cooling fluid passes; a rotor coupled to a center of the stator to rotate; and a housing coupled to left and right sides of the stator to form a cooling jacket in watertight communication with a cooling slot so that a cooling fluid circulates in the cooling jacket.

Abstract: Disclosed are a hybrid solid electrolyte sheet and a method of manufacturing the same. The hybrid solid electrolyte sheet includes a hybrid solid electrolyte layer including a gel polymer electrolyte, thereby securing flexibility and alleviating brittleness. In addition, the hybrid solid electrolyte sheet includes a porous polymer film having a plurality of pores, thus minimizing the content of the acrylate monomer in the pores thereof and providing advantages of maintaining the continuity of the solid electrolyte while minimizing a decrease in ionic conductivity.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.