Patents by Inventor Hoon-joo Na
Hoon-joo Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967595Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: GrantFiled: September 30, 2020Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
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Patent number: 11728200Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.Type: GrantFiled: December 4, 2019Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
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Patent number: 11588039Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: GrantFiled: November 25, 2019Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong Lee, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Publication number: 20220375983Abstract: An image sensor is provided. The image sensor includes unit pixels inside the substrate; a pixel separation pattern provided between the unit pixels, inside the substrate; a first inter-wiring insulating film provided on the first surface of the substrate; a pad pattern provided inside the first inter-wiring insulating film; a first connection pattern provided inside the first inter-wiring insulating film, an upper surface of the first connection pattern and an upper surface of the first inter-wiring insulating film being provided along a first common plane; a second inter-wiring insulating film provided on the upper surface of the first inter-wiring insulating film; a second connection pattern provided inside the second inter-wiring insulating film, a lower surface of the second connection pattern and a lower surface of the second inter-wiring insulating film being provided along a second common plane; and a microlens provided on the second surface of the substrate.Type: ApplicationFiled: January 12, 2022Publication date: November 24, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Kuk Kang, Min Ho Jang, Hoon Joo Na, Hee Ju Shin
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Patent number: 11495597Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.Type: GrantFiled: September 24, 2020Date of Patent: November 8, 2022Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
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Patent number: 11417536Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.Type: GrantFiled: June 12, 2019Date of Patent: August 16, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joo Hee Jang, Seok Ho Kim, Hoon Joo Na, Kwang Jin Moon, Jae Hyung Park, Kyu Ha Lee
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Publication number: 20220130884Abstract: An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.Type: ApplicationFiled: August 4, 2021Publication date: April 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Shik KIM, Min-Sun KEEL, Hoon Joo NA, Kang Ho LEE, Kil Ho LEE, Sang Kil LEE, Jung Hyuk LEE, Shin Hee HAN
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Patent number: 11283235Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.Type: GrantFiled: August 12, 2019Date of Patent: March 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hoe-Chul Kim, Hoon-Joo Na
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Patent number: 11177364Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: July 24, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Patent number: 11133277Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.Type: GrantFiled: July 31, 2019Date of Patent: September 28, 2021Inventors: Jin Nam Kim, Tae Seong Kim, Hoon Joo Na, Kwang Jin Moon
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Patent number: 10906283Abstract: A wafer bonding apparatus including: a lower chuck to which a lower wafer is secured at a peripheral portion of the lower chuck; an upper chuck to which an upper wafer is secured; a bonding initiator for pressuring a central portion of the upper wafer until the central portion of the upper wafer reaches a central portion of the lower wafer, thereby initiating a bonding process of the upper and the lower wafers by deforming the upper wafer; and a bonding controller for controlling a bonding speed between a peripheral portion of the upper wafer and a peripheral portion of the lower wafer such that the upper wafer becomes un-deformed prior to bonding the peripheral portion of the upper wafer and the peripheral portion of the lower wafer.Type: GrantFiled: April 17, 2019Date of Patent: February 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Yeong Kim, Jun-Hyung Kim, Hoe-Chul Kim, Hoon-Joo Na, Kwang-Jin Moon
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Publication number: 20210020631Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
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Publication number: 20210013207Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Jae Jung KIM, Young Suk CHAI, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN
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Patent number: 10872888Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.Type: GrantFiled: June 5, 2019Date of Patent: December 22, 2020Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
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Publication number: 20200373186Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.Type: ApplicationFiled: December 4, 2019Publication date: November 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
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Patent number: 10847515Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.Type: GrantFiled: November 29, 2018Date of Patent: November 24, 2020Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
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Publication number: 20200365706Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: ApplicationFiled: July 24, 2020Publication date: November 19, 2020Inventors: Byoung-Hoon Lee, HOON-JOO NA, SUNG-IN SUH, MIN-WOO SONG, CHAN-HYEONG LEE, HU-YONG LEE, SANG-JIN HYUN
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Patent number: 10756195Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: November 2, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Publication number: 20200243466Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.Type: ApplicationFiled: July 31, 2019Publication date: July 30, 2020Inventors: Jin Nam Kim, Tae Seong Kim, Hoon Joo Na, Kwang Jin Moon
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Publication number: 20200168471Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane regionType: ApplicationFiled: June 12, 2019Publication date: May 28, 2020Inventors: JOO HEE JANG, Seok Ho Kim, Hoon Joo NA, Kwang Jin Moon, Jae Hyung Park, Kyu Ha Lee