Abstract: An apparatus and method for automatically focusing a miniature digital camera module (MUT) is described. A MUT is loaded onto a test fixture and aligned with an optics system of a test handler. Focus targets contained within two target wheels are positioned over an optical centerline above the digital camera module using stepper motors. A field lens is positioned to focus an image of the targets onto the lens opening of the MUT. The image can be of a single target or a combination of targets contained on the target wheels at various optical distances from the MUT. A focusing unit adjusts the lens cap of the MUT for a best focus setting and after the MUT has been tested the best focus setting if physically fixed by permanently connecting the lens cap to the body of the MUT.

Abstract: An intelligent light source for use with the test of a digital camera module provides a plurality of shapes of light. A fast light pulse is created with turn-on and turn-off transitions less than or equal to one microsecond. Other waveform shapes comprise a ramp and a sinusoid, and all shapes can be made to occur once or repetitively. The magnitude of the light has a range from 0.01 LUX to 1000 LUX, and the ramp has a ramp time that has a range from microseconds to 100 ms. The light comprises of a plurality of colors created by serial connected strings of LED devices, where the LED devices in a string emit the same color. The light emanating from the light source is calibrated using a photo diode and the control of a tester by adjusting offset voltages of a DAC controlling a current through the LED strings.

Abstract: A test handler is controlled by a tester to transport, select, focus and test miniature digital camera modules. The modules are loaded onto a transport tray and moved on a conveyer to a robot. The robot selects the untested modules from the tray an alternately places the modules into two test stations. A first test station focuses and tests a first module while the second test station is loaded with a second module, thus burying the handling time for the modules within the test time. The robot returns tested modules to the transport tray, and when all modules on the tray are tested, moves the tray out of the test handler. A second tray with untested modules is positioned at the robot while the tested modules of the first tray are being focus fixed and sorted into part number bins. The overlap of operations buries handling time within the focus and test time so that the limitation of total test time is depending on focus and test operations.

Abstract: Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Abstract: Circuits and related methods for switched step-down and boost DC-to-DC converters have been achieved. Said DC-to-DC converters comprise an inductor current sensing and limiting circuit to prevent the inductor current to exceed a defined limit. Said current sense circuit is using the voltage on the on-state source-to-drain resistance of a power switch to monitor the inductor current. Said voltage is amplified and serves as input of a regulator. Said regulator, being connected via one or more gate controllers to the gates of said power switches, controls the ON/OFF state of said power switches by pulse-width-modulation. Said power switches are switched ON/OFF if the current exceeds a defined limit. After a defined time period said power switches are switched on again. Gate controllers keep the power switch in an operating region having a stable source-to drain resistance while said power switch is ON.

Abstract: Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Abstract: A digital color imager providing an extended luminance range, an improved color implementation and enabling a method for an easy transformation into another color space having luminance as a component has been achieved. Key of the invention is the addition of white pixels to red, green and blue pixels. These white pixels have either an extended dynamic rang as described by U.S. patent (U.S. Pat. No. 6,441,852 to Levine et al.) or have a larger size than the red, green, or blue pixels used. The output of said white pixels can be directly used for the luminance values Y of the destination color space. Therefore only the color values and have to be calculated from the RGB values, leading to an easier and faster calculation. As an example chosen by the inventor the conversion to YCbCr color space has been shown in detail.

Abstract: A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.

Abstract: A circuit and a method to measure continuously the resistance of variable resistors in series as e.g. potentiometers within a sensor, used for e.g. a joystick, has been achieved. The voltage across said sensor comprising any number of variable resistors is stabilized. A constant current source is providing a minimum current through said sensor. A variable current source is used to zoom variations of current through the sensor caused by variations of resistance of the sensor. Said variable current is mirrored and by measuring the voltage across a shunt resistor the total resistance of the sensor is identified. Using ports between each of the resistors, voltages can be measured representing the resistance of each of the variable resistors using known equations of voltage dividers. Any number of variable resistors can be used in the circuit invented.

Abstract: A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.

Abstract: A semiconductor device for reducing the chip-area on an integrated circuit required for multiple, cascaded MOS transistors, a method of designing said devices and an exemplary portions of circuits using said devices have been achieved. Said novel semiconductor device comprises multiple MOS transistors sharing one common well, one common bulk and are sharing between adjacent MOS transistors each a doped area used as a drain of one transistor and as a source for the other transistor. The chip-area required for the transistors itself of the invented semiconductor device is significantly smaller than the chip-area of conventional transistors having a single well for each transistor. Said MOS transistors, sharing one common well, could be either PMOS transistors or NMOS transistors. The breakdown voltages of said semiconductor device is significantly higher compared to conventional MOS transistors.

Abstract: In a Class-D Amplifier with PCM (Pulse Code Modulated) input signal, the output pulse width may be adjusted to provide a constant time-voltage-area or the output pulse width may have one of several discrete values to provide a multi-level output system. A fundamental idea of this disclosure is to assure the center of each output pulse is always positioned at the nominal clock or with a fixed delay relative to the nominal clock. Said Class-D Amplifier typically converts the input signal into PDM (Pulse Density Modulated) pulses with a Sigma Delta Modulator and typically drives the output load with an H-Bridge.

Abstract: Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Abstract: A circuit and method are given, to realize a loudness control for mobile phone earpieces and speakers with the help of a proximity sensor, which is realized as an infrared photo-electric guard circuit, where only very few external parts are needed. As a novelty here, the necessary photo sensors are integrated onto a single chip. To form the photodiodes within a single IC together with the other circuit elements are much less expensive. Using the advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only very few discrete external components. This solution reduces also power consumption and manufacturing cost.

Abstract: A circuit and method are given, to realize a high-voltage control and driver interface as integrated circuit, especially for use in connection with four external components, inductor L and capacitor C as well as low-side and high-side switching transistors as found e.g. in half-bridges. The circuit is essentially self supplied by means of an Intrinsically floating auxiliary supply power generation and regulation scheme. The circuit is apt to supporting high main supply voltages up to 1000V. The circuit of the invention is realized without the need for any internal high-voltage integrated semiconductor devices. Exploiting the advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete external components, which is favorably lowering the cost of production.

Abstract: A circuit and a method to measure continuously the resistance of variable resistors in series as e.g. potentiometers within a sensor, used for e.g. a joystick, has been achieved. The voltage across said sensor comprising any number of variable resistors is stabilized. A constant current source is providing a minimum current through said sensor. A variable current source is used to zoom variations of current through the sensor caused by variations of resistance of the sensor. Said variable current is mirrored and by measuring the voltage across a shunt resistor the total resistance of the sensor is identified. Using ports between each of the resistors, voltages can be measured representing the resistance of each of the variable resistors using known equations of voltage dividers. Any number of variable resistors can be used in the circuit invented.

Abstract: A method to linearize the characteristic of a Class-D amplifier is achieved, by compensating for the pulse-area-error, caused by a non-constant power-supply and similar circuit inconsistencies. A Class-D Amplifier typically converts the PDM (Pulse Density Modulated) input signal with a Sigma Delta Modulator and typically uses an H-Bridge as the Class-D power output stage. A fundamental idea is to keep the time-voltage area of every pulse constant. To achieve this, the circuit integrates the power supply voltage, starting with the PDM input pulse and stopping, when the defined time-voltage reference is reached. To compensate not only for power supply variations, but also for e.g. the voltage drop across the output devices, the integrator's input would be more directly reference to the actual voltage across the output load.

Abstract: A method for compensating for the pulse area error of a Class-D power amplifier is achieved; especially it compensates the variations in the supply voltage and similar dependencies. A Class-D Amplifier typically gets pulse coded digital input (PCM) and may comprise a Sigma Delta Modulator to generate the signals driving the power output stage, typically an H-Bridge. A fundamental idea of this invention is to measure the real area of the output pulses, where the area is defined as the pulse duration multiplied by the pulse voltage amplitude, and to compare it with the ideal nominal pulse area. The pulse area error is calculated and then subtracted from said amplifier's input data. Key element of this invention is the “Pulse Area Compensation Function”, which calculates said real pulse area (voltage amplitude multiplied by time), compares said real pulse area with said ideal pulse area and feeds the difference into the input of said Sigma Delta Modulator.

Abstract: In a Class-D Amplifier with PCM (Pulse Code Modulated) input signal, the output pulse width may be adjusted to provide a constant time-voltage-area or the output pulse width may have one of several discrete values to provide a multi-level output system. A fundamental idea of this disclosure is to assure the center of each output pulse is always positioned at the nominal clock or with a fixed delay relative to the nominal clock. Said Class-D Amplifier typically converts the input signal into PDM (Pulse Density Modulated) pulses with a Sigma Delta Modulator and typically drives the output load with an H-Bridge.

Abstract: An energy control circuit for a class D amplifier is achieved. The energy control circuit comprises, first, a means of generating an energy accumulation signal proportional to an output drive signal of the class D amplifier. Last, a means of receiving the energy accumulation signal and of interrupting the output drive signal when the energy accumulation signal exceeds a reference level. Single-ended and H-bridge amplifiers are achieved.