Patents by Inventor Hosadurga K. Shobha
Hosadurga K. Shobha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11232983Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: September 3, 2020Date of Patent: January 25, 2022Assignee: Tessera, Inc.Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 11177167Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: GrantFiled: May 10, 2016Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Daniel Edelstein, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Publication number: 20200402848Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 10770347Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: October 18, 2019Date of Patent: September 8, 2020Assignee: Tessera, Inc.Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 10643890Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.Type: GrantFiled: May 10, 2016Date of Patent: May 5, 2020Assignee: International Business Machines CorporationInventors: Daniel Edelstein, Alfred Grill, Seth L. Knupp, Son Nguyen, Takeshi Nogami, Vamsi K. Paruchuri, Hosadurga K. Shobha, Chih-Chao Yang
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Patent number: 10593591Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: August 31, 2018Date of Patent: March 17, 2020Assignee: Tessera, Inc.Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Publication number: 20200051854Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Patent number: 10325806Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: November 29, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 10256185Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.Type: GrantFiled: October 25, 2017Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chih-Chao Yang
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Patent number: 10224241Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: November 29, 2017Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Publication number: 20180374748Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Patent number: 10157789Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: GrantFiled: August 17, 2016Date of Patent: December 18, 2018Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., STMicroelectronics, Inc.Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Patent number: 9966337Abstract: A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the second metallization layer interconnects adjacent one another and surrounded by the first metallization layer interconnects and a cap. The first and second metallization layer interconnects have respective upper surfaces defining a first plane and a second plane recessed from the first plane, respectively. The cap is disposed on exposed surfaces of the second metallization layer interconnects and portions of the dielectric layer adjacent to the second metallization layer interconnects.Type: GrantFiled: March 15, 2017Date of Patent: May 8, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga K. Shobha
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Patent number: 9947579Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: January 27, 2017Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 9947581Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: July 20, 2016Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Publication number: 20180090371Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: November 29, 2017Publication date: March 29, 2018Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Publication number: 20180090436Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.Type: ApplicationFiled: October 25, 2017Publication date: March 29, 2018Inventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chi-Chao Yang
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Publication number: 20180082894Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: November 29, 2017Publication date: March 22, 2018Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Patent number: 9899317Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.Type: GrantFiled: September 29, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chi-Chao Yang
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Publication number: 20170140981Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA