Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

Abstract: A device includes a channel layer, a gate structure, a first source/drain structure, a second source/drain structure, and a backside via. The gate structure surrounds the channel layer. The first source/drain structure and the second source/drain structure ate connected to the channel layer. The backside via is connected to a backside of the first source/drain structure. The backside via includes a first portion, a second portion, and a third portion. The first portion is connected to the backside of the first source/drain structure. The third portion tapers from the second portion to the first portion. A sidewall of the third portion is more inclined than a sidewall of the second portion.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

Abstract: A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.

Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

Abstract: A method for manufacturing a semiconductor structure is provided. A first layout is received, wherein the first layout comprises at least a pattern of an active region extending in a first direction. A second layout comprising a plurality of gate patterns extending in a second direction substantially perpendicular to the first direction is received, wherein distances between adjacent gate patterns are substantially consistent among the plurality of gate patterns. The first layout and the second layout are overlapped, thereby forming a plurality of transistor patterns. One of the plurality of gate patterns is shifted toward a source of one of the transistor patterns to form a third layout. A first photomask including the third layout is formed. The third layout of the photomask is transferred to form a plurality of gate structures over a substrate. A semiconductor structure thereof is also provided.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.

Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively. The first and second S/D epitaxial features have a first conductivity type. The semiconductor device also includes a stack of second channel layers stacked over the first channel layers and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively. The third and fourth S/D epitaxial features have a second conductivity type. A total active channel layer number of the first channel layers is different from that of the second channel layers.

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.

Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.

Abstract: A semiconductor device includes a channel region, first and second S/D contacts, first and second S/D epitaxial regions, a gate structure, and a gate contact. The channel region includes a first surface, a second surface opposite to the first surface, and a sidewall connected to the first surface and the second surface. The first S/D contact is disposed over the first surface of the channel region, the second S/D contact is disposed underneath the second surface of the channel region, the first S/D epitaxial region underlies the first S/D contact and overlies the first surface of the channel region, and the second S/D epitaxial region overlies the second S/D contact and underlies the second surface of the channel region. The gate structure surrounds the sidewall of the channel region, and the gate contact is disposed in proximity to the second S/D contact and lands on the gate structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.