Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

Abstract: A method for manufacturing a semiconductor structure is provided. A first layout is received, wherein the first layout comprises at least a pattern of an active region extending in a first direction. A second layout comprising a plurality of gate patterns extending in a second direction substantially perpendicular to the first direction is received, wherein distances between adjacent gate patterns are substantially consistent among the plurality of gate patterns. The first layout and the second layout are overlapped, thereby forming a plurality of transistor patterns. One of the plurality of gate patterns is shifted toward a source of one of the transistor patterns to form a third layout. A first photomask including the third layout is formed. The third layout of the photomask is transferred to form a plurality of gate structures over a substrate. A semiconductor structure thereof is also provided.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.

Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively. The first and second S/D epitaxial features have a first conductivity type. The semiconductor device also includes a stack of second channel layers stacked over the first channel layers and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively. The third and fourth S/D epitaxial features have a second conductivity type. A total active channel layer number of the first channel layers is different from that of the second channel layers.

Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.

Abstract: A semiconductor device includes a channel region, first and second S/D contacts, first and second S/D epitaxial regions, a gate structure, and a gate contact. The channel region includes a first surface, a second surface opposite to the first surface, and a sidewall connected to the first surface and the second surface. The first S/D contact is disposed over the first surface of the channel region, the second S/D contact is disposed underneath the second surface of the channel region, the first S/D epitaxial region underlies the first S/D contact and overlies the first surface of the channel region, and the second S/D epitaxial region overlies the second S/D contact and underlies the second surface of the channel region. The gate structure surrounds the sidewall of the channel region, and the gate contact is disposed in proximity to the second S/D contact and lands on the gate structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A semiconductor device includes semiconductor nanosheets, a gate structure, and a dielectric spacer. The semiconductor nanosheets are vertically stacked over each other, disposed above a semiconductor substrate, and serve as channel regions. A bottommost semiconductor nanosheet most proximate from the semiconductor substrate is a thinnest nanosheet of the semiconductor nanosheets. The gate structure surrounds each of the semiconductor nanosheets in a first cross-section, and the dielectric spacer is interposed between the bottommost semiconductor nanosheet and the semiconductor substrate and adjoins the gate structure in the first cross-section.

Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.