Abstract: A motherboard includes at least one backup network circuit except for a network circuit used in a normal setup. The motherboard includes a first network circuit, a second network circuit, a network port, a switch circuit and a driver. The switch circuit is configured for coupling the first network circuit or the second network circuit to the network port. The driver is configured for switching the switch circuit according to states of the network port and the first network circuit.

Abstract: A motherboard includes a first chipset, a second chipset, a central processing unit (CPU), a low-speed bus, a first switch circuit and a second switch circuit. In a normal setup, the first switch circuit is coupled to the first chipset and the CPU, and the second switch circuit is coupled to the first chipset and the low-speed bus. In a backup setup, the first switch circuit is coupled to the second chipset and the CPU, and the second switch circuit is coupled to the second chipset and the low-speed bus. The motherboard of the present invention further comprises a switch-circuit control unit or a driver configured for switching the first and second switch circuits to be in the backup setup when the first chipset is damaged in the normal setup.

Abstract: An automatic network connection device includes a first connection port, a second connection port, a first network connection unit, a second network connection unit, a control unit, and a switching unit. When the first network connection unit operates normally, the switching unit electrically connects the first network connection unit to the first connection port, such that the first network connection unit transmits and receives a network signal. When the first network connection unit fails, the switching unit switches the first connection port to be electrically connected to the second network connection unit, such that the second network connection unit transmits and receives the network signal.

Abstract: A method for power management of a motherboard is provided to manage a power supply on the motherboard and specially to manage an output power of a power management module on the mother board. The motherboard at least comprises a microprocessor, and the power management module provides a power with a number of output phases to the microprocessor. First, a first load of the microprocessor is detected in a first time. Then a second load of the microprocessor in a second time is detected. When the second load is less than the first load and is lower than a first predetermined value, the number of output phases of the power outputted from the power management module is reduced.

Abstract: A method for automatically restoring a system configuration with a single key in a computer having a power button is provided. The method includes detecting a press mode of the power button; determining a relevant restoring item according to the press mode; performing a process for restoring the system configuration corresponding to the restoring item, which aims at updating/recovering the system configuration, or clearing the system configuration setting stored in a CMOS memory; and performing a normal boot process.

Abstract: A system for detecting a peripheral device is used to detect whether the peripheral device is completely inserted into a peripheral interface slot of a mother board before booting. When the peripheral device is inserted into the peripheral interface slot, the system judges whether the peripheral device is completely inserted into the peripheral interface slot according to a potential of fins of the peripheral interface slot. If the system detects that the peripheral device has not been completely inserted into the peripheral interface slot before booting, a booting procedure of the mother board is interrupted and an alarm signal is output.

Abstract: A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.

Abstract: A structure of an interface card connector includes a connector body and a plurality of terminals provided on the connector body. The bottom surface of the connector body is divided into a terminal zone and a space zone along the transverse direction. The distal ends of the terminals project from the terminal zone toward the bottom surface of the connector body. The space zone is recessed toward the connector body to form a notch portion, so that the bottom surface formed by the space zone is higher than that formed by the terminal zone. The space zone is used to provide a space for arranging the electronic components on the main board, so that more space on the main board is spared for the circuit layout. With this arrangement, the problem of the insufficient space and area of the main board can be solved.

Abstract: A structure of an interface card connector includes a connector body and a plurality of terminals provided on the connector body. The bottom surface of the connector body is divided into a terminal zone and a space zone along the transverse direction. The distal ends of the terminals project from the terminal zone toward the bottom surface of the connector body. The space zone is recessed toward the connector body to form a notch portion, so that the bottom surface formed by the space zone is higher than that formed by the terminal zone. The space zone is used to provide a space for arranging the electronic components on the main board, so that more space on the main board is spared for the circuit layout. With this arrangement, the problem of the insufficient space and area of the main board can be solved.

Abstract: A computer system has a central processing unit (CPU), and a chipset for supporting the CPU, and a selectable BIOS system. The chipset has a first general purpose input/output (GPIO) register. The selectable BIOS includes a primary and secondary BIOS programs, a timer circuit for generating a delay signal after power-on of the computer system, and a BIOS switching circuit. The primary BIOS program has confirmation code for generating a confirmation signal on the first GPIO register. The BIOS switching circuit shadows the primary or secondary BIOS program into a predetermined address space of the CPU according to the confirmation signal and the delay signal. While the primary BIOS program is shadowed, if the BIOS switching circuit receives the timer delay signal before receiving the BIOS confirmation signal, then the BIOS switching circuit causes the CPU to be reset and shadows the secondary BIOS program.

Abstract: A management system is provided for access control modes of a dynamic random access memory (DRAM) module socket. The management system includes a basic input/output system (BIOS), an integrated chipset, two switches, and a DRAM module socket. The two switches are respectively connected between an ECC/CKE and a DQM/CKE mode output port of the integrated chipset, and an ECC, a CKE, and a DQM mode input port of the DRAM module socket. The management system utilizes general purpose input/output (GPIO) terminals of the integrated chipset to control on/off states of the two switches so as to switch between both the ECC, the CKE, and the DQM mode input ports of the DRAM module socket. Software reconfigurations, by way of the BIOS, for DRAM access control modes are thus made possible.

Abstract: A computer system has a central processing unit (CPU), and a chipset for supporting the CPU, and a selectable BIOS system. The chipset has a first general purpose input/output (GPIO) register. The selectable BIOS includes a primary and secondary BIOS programs, a timer circuit for generating a delay signal after power-on of the computer system, and a BIOS switching circuit. The primary BIOS program has confirmation code for generating a confirmation signal on the first GPIO register. The BIOS switching circuit shadows the primary or secondary BIOS program into a predetermined address space of the CPU according to the confirmation signal and the delay signal. While the primary BIOS program is shadowed, if the BIOS switching circuit receives the timer delay signal before receiving the BIOS confirmation signal, then the BIOS switching circuit causes the CPU to be reset and shadows the secondary BIOS program.