Patents by Inventor Houde Zhou

Houde Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167039
    Abstract: A chip package structure including a first chip stack and a redistribution layer is provided. The first chip stack includes a plurality of first chips, a first molding layer and at least one first vertical conductive element. The plurality of first chips are sequentially stacked, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pads are not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element penetrates through the first molding layer, wherein the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.
    Type: Application
    Filed: January 7, 2020
    Publication date: June 3, 2021
    Inventors: XinRu Zeng, Peng Chen, Houde Zhou
  • Publication number: 20210082838
    Abstract: An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached.
    Type: Application
    Filed: November 3, 2019
    Publication date: March 18, 2021
    Inventors: Peng Chen, Houde Zhou, Chao Gu
  • Publication number: 20200335410
    Abstract: A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 22, 2020
    Inventors: Peng Chen, Houde Zhou, BaoHua Zhang, Chao Gu
  • Publication number: 20200235023
    Abstract: An integrated circuit (IC) packaging structure includes a packaging substrate, one or a plurality of dies, an encapsulation material, at least one trench, and a heat dissipation structure. The one or the plurality of the dies is disposed on the packaging substrate. The encapsulation material is disposed on the packaging substrate and is configured to encapsulate the one or the plurality of the dies on the packaging substrate. The at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench. The cooling capability of the IC packaging structure may be improved by the heat dissipation structure without increasing the size of the IC packaging structure significantly.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 23, 2020
    Inventors: Peng Chen, Houde Zhou, BaoHua Zhang, Chao Gu
  • Publication number: 20200135656
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) package. The IC package includes a package substrate, one or more IC chips, a marking plate and a plastic structure. The one or more IC chips are interconnected with the package substrate. The marking plate has a first major surface and a second major surface. The marking plate is stacked on the one or more IC chips with the first major surface facing the one or more IC chips. The plastic structure is configured to encapsulate the one or more IC chips and the marking plate with the second major surface of the marking plate being a portion of an outer surface of the IC package.
    Type: Application
    Filed: March 27, 2019
    Publication date: April 30, 2020
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Houde Zhou, Peng Chen