Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.

Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.

Abstract: Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.

Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.

Abstract: A routing layer for a microelectronic device includes a first region (110, 510) containing a first trench (111, 511), a second region (120, 520) containing a second trench (121, 521), and an electrically conductive material (230, 530) in the first trench and in the second trench. The first trench has a first depth (115) and the second trench has a second depth (125) that is different from the first depth.

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

Abstract: Disclosed are a coreless substrate and a method of manufacturing the same. The coreless substrate includes a solder resist layer capable of being formed on each of on a first side and a second side of a metal panel. The solder resist layer includes at least one opening. A copper layer may be plated in the at least one opening such that a height of the copper layer exceeds a height of the solder resist layer. Further, at least one dielectric layer is deposited above the copper layer, and at least one microvia drilled in the dielectric layer. The at least one microvia enables an electrical connection between at least one of the first side and the second side of the metal panel and a lower surface of the coreless substrate.

Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

Abstract: Microball delivery solutions for solder bumping are generally described. In this regard, according to one example embodiment, a microball delivery assembly includes a mask with at least two microball holder(s) to hold at least two different sizes of microball(s) that may correspond with at least two different-sized openings on a substrate, to provide simultaneous delivery of different-sized microballs upon a substrate.

Abstract: A method of removing unwanted material from a substrate includes providing a system (600) having an etchant solution (610) with an electrode (620) therein and a current supply (630) connected to the electrode, placing the substrate in the solution and connecting it to the current supply, providing an electric current to the electrode, and altering a polarity of the electric current such that the substrate experiences an anodic polarity for a first time period and a cathodic polarity for a shorter time period. An alternative method includes providing a solution delivery system (1100) having a second etchant solution (1110) with an eductor jet (1140) therein and a recirculation pump connected to the eductor jet, placing the substrate in the second solution, and using the eductor jet to spray the substrate with the second solution. If desired, both methods may be used.

Abstract: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the resist assembly. A solder bump is formed on the SR opening. The PEMU is removed.

Abstract: Microball delivery solutions for solder bumping are generally described. In this regard, according to one example embodiment, a microball delivery assembly includes a mask with at least two microball holder(s) to hold at least two different sizes of microball(s) that may correspond with at least two different-sized openings on a substrate, to provide simultaneous delivery of different-sized microballs upon a substrate.

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.