Patents by Inventor Howard E. Rhodes

Howard E. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench photosensor for a CMOS imager
    Patent number: 7445951
    Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Image sensor pixel having photodiode with indium pinning layer
    Patent number: 7432543
    Abstract: An active pixel using a pinned photodiode with a pinning layer formed from indium is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. A pinning layer formed from indium is then formed at the surface of the N? region. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: October 7, 2008
    Assignee: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes
  • WAVEGUIDE FOR THERMO OPTIC DEVICE
    Publication number: 20080226247
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Image device and photodiode structure
    Patent number: 7422924
    Abstract: The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation region. These dopant ions are further surrounded by dopant ions of the first conductivity type with a second impurity concentration. The resulting isolation region structure increases the capacitance of the photodiode by allowing the photodiode to possess a greater charge collection region while suppressing the generation of dark current.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: September 9, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Photodiode for improved transfer gate leakage
    Patent number: 7420233
    Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: September 2, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Howard E. Rhodes, Richard A. Mauritzson, Inna Patrick
  • Pinned photodiode structure and method of formation
    Publication number: 20080188029
    Abstract: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.
    Type: Application
    Filed: April 7, 2008
    Publication date: August 7, 2008
    Inventor: Howard E. Rhodes
  • CMOS imager with selectively silicided gate
    Patent number: 7405101
    Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: July 29, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
    Publication number: 20080176350
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Application
    Filed: March 20, 2008
    Publication date: July 24, 2008
    Inventor: Howard E. Rhodes
  • Optimized transistor for imager device
    Patent number: 7402451
    Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • IMAGE SENSOR PIXEL HAVING PHOTODIODE WITH MULTI-DOPANT IMPLANTATION
    Publication number: 20080164501
    Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.
    Type: Application
    Filed: March 18, 2008
    Publication date: July 10, 2008
    Applicant: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes
  • IMAGE SENSOR PIXEL HAVING PHOTODIODE WITH MULTI-DOPANT IMPLANTATION
    Publication number: 20080166830
    Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.
    Type: Application
    Filed: March 18, 2008
    Publication date: July 10, 2008
    Applicant: OmniVision Technologies, Inc.
    Inventor: Howard E. Rhodes
  • Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
    Patent number: 7397075
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Imager light shield
    Patent number: 7390690
    Abstract: An improved imager pixel arrangement having a light shield over the pixel circuitry, but below the conductive interconnect layers of the pixel. The light shield can be a thin film of opaque (or nearly-opaque) material with openings for contacts to the underlying circuitry. An aperture in the light shield exposes the active region of the pixel's photoconversion device.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Pinned photodiode structure and method of formation
    Patent number: 7388241
    Abstract: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Local multilayered metallization
    Patent number: 7388289
    Abstract: An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having a trench including a metal layer and a second trench including a plurality of metal layers coupled to the metal layer is disclosed. The metal layer is highly conductive, and at least one of the plurality of metal layers is a metal layer that is capable of being reliably wire-bonded to a gold wire. The trench is narrower than the second trench, and at least one of the plurality of metal layers is copper or a copper alloy.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Pinned photodiode structure and method of formation
    Patent number: 7378696
    Abstract: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Pinned photodiode structure and method of formation
    Patent number: 7378697
    Abstract: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of a substrate and a graded pinned surface layer, self-aligned to a gate stack is provided. These photodiodes exhibit reduced image lag, transfer gate leakage, and photodiode dark current generation.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Local multilayered metallization
    Patent number: 7375026
    Abstract: An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a function of the width. In an alternate embodiment, a metallization structure having a trench including a metal layer and a second trench including a plurality of metal layers coupled to the metal layer is disclosed. The metal layer is highly conductive, and at least one of the plurality of metal layers is a metal layer that is capable of being reliably wire-bonded to a gold wire. The trench is narrower than the second trench, and at least one of the plurality of metal layers is copper or a copper alloy.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
    Patent number: 7368339
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Waveguide for thermo optic device
    Patent number: 7359607
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried