Abstract: A pixel for an imaging device is described. The pixel includes a photosensitive device provided within a substrate for providing photo-generated charges, a circuit associated with the photosensitive device for providing at least one pixel output signal representative of the photo-generated charges, the circuit includes at least one operative device that is responsive to a first control signal during operation of the associated circuit and a pump circuit. The pump circuit may include substrate pumps, charge pumps and/or voltage pumps. The pixel may also be embedded in an imaging system.

Abstract: A color pixel array includes first, second, and third pluralities of color pixels each including a photosensitive region disposed within a first semiconductor layer. In one embodiment, a second semiconductor layer including deep dopant regions is disposed below the first semiconductor layer. The deep dopant regions each reside below a corresponding one of the first plurality of color pixels but substantially not below the second and third pluralities of color pixels. In one embodiment, buried wells are disposed beneath the second and third pluralities of color pixels but substantially not below the first plurality of color pixels.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Abstract: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening.

Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Abstract: An active pixel using a transfer gate that has a polysilicon gate doped with P+ is disclosed. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the floating node and the photosensitive element. The transfer gate is doped with a p-type dopant.

Abstract: A photogate structure having increased quantum efficiency, especially for low wavelength light such as blue light. The photogate is formed of a thin conductive layer, such as a layer of doped polysilicon. A nitride insulating cap is formed over the conductive layer. The nitride layer reduces the reflections at the conductor/insulator interface. A pixel cell incorporating the photogate structure also has a buried accumulation region beneath the photogate. A method of fabricating the photogate structure is also disclosed.

Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.

Abstract: An active pixel using a transfer gate that has a polysilicon gate doped with indium. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the floating node and the photosensitive element. The pixel substrate has a laterally doping gradient doped with an indium dopant.

Abstract: An image sensor includes an optical sensor region, a stack of dielectric and metal layers, and an embedded layer. The optical sensor is disposed within a semiconductor substrate. The stack of dielectric and metal layers are disposed on the front side of the semiconductor substrate above the optical sensor region. The embedded focusing layer is disposed on the backside of the semiconductor substrate in a Backside Illuminated (BSI) image sensor, supported by a support grid, or a support grid composed of the semiconductor substrate.

Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface latter has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.

Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.

Abstract: The disclosure describes embodiments of a process comprising forming a pixel on a frontside of a substrate, the substrate having a frontside, a backside, and a thickness substantially equal to a distance between the frontside and the backside. The thickness of the substrate is reduced by removing material from the backside of the substrate to allow for backside illumination of the pixel, and the backside of the substrate is treated with a hydrogen plasma to passivate the backside. The disclosure also describes embodiments of an apparatus comprising a semiconductor wafer having a frontside, a backside, and a thickness substantially equal to a distance between the frontside and the backside, and a pixel formed on the frontside, wherein the thickness of the wafer is selected and adjusted to allow for illumination of the pixel through the backside of the wafer, and wherein the backside is treated with a hydrogen plasma to passivate the backside.

Abstract: Embodiments of the invention provide pixel cells that allow both automatic light control and correlated double sampling operations. The pixel cell includes first and second photo-conversion devices that can be separately read out. For example, the second photo-conversion device can be the pixel cells' floating diffusion region, with an area and doping profile suitable for photo-conversion. An image sensor may include an array of pixel cells, some or all of which have two photo-conversion devices, and peripheral circuitry for reading out signals from the pixel cells. The image sensor's readout circuitry may monitor charge generated by the second photo-conversion devices to determine when to read out signals from the first photo-conversion devices.

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: An image sensor includes a substrate having a surface at which incident light is received. A pixel array is formed over and within the substrate. The pixel array includes a first and a second pixel arranged to receive light of different colors. The first pixel includes a photosensitive region formed in the substrate and has a first anti-reflective coating (ARC) layer formed over the photosensitive region. The first ARC layer has a first thickness that produces destructive interference above the first ARC layer in response to the incident light. The second pixel includes a photosensitive region formed in the substrate, and a second ARC layer formed over the photosensitive region that produces destructive interference above the second ARC layer in response to the incident light.

Abstract: An image sensor with a high full-well capacity includes a photosensitive region, a transfer gate, and sidewall spacers. The photosensitive region is formed to accumulate an image charge in response to light. The transfer gate disposed adjacent to the photosensitive region and coupled to selectively transfer the image charge from the photosensitive region to other pixel circuitry. First and second sidewall spacers are disposed on either side of the transfer gate. The first sidewall spacer closest to the photosensitive region is narrower than the second sidewall spacer. In some cases, the first sidewall spacer may be omitted.

Abstract: An imaging circuit includes a pixel array that is arranged to concurrently reset pixels in a pixel array in response to a global reset signal. The pixels are arranged in rows, such that the rows can be individually selected by a row select line. A reset transistor concurrently resets the pixels by coupling a reset voltage to a floating diffusion of the pixel. A transfer gate transistor selectively couples the floating diffusion to a storage region. A storage gate transistor selectively couples the storage region to a photosensitive region so that the reset transistor, the transfer gate transistor, and the storage gate transistor for each of the pixels can be activated in response to the global reset signal. A double correlated sampler may be used to provide a correlated double sample using a first sampled voltage of a reset voltage and a second sampled voltage of a pixel voltage that is produced when a photodiode region is exposed to incident light.

Abstract: A transistor contact over a gate active area includes a transistor gate formed on a substrate of an integrated circuit. A gate insulator is formed beneath the transistor gate and helps define an active area for the transistor gate. An insulating layer is formed over the transistor gate. A metal contact plug is formed within a portion of the insulating layer that lies over the active area such that the metal contact plug forms an electrical contact with the transistor gate.