Patents by Inventor Howard H. Chen
Howard H. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10725755Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: GrantFiled: June 6, 2017Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffrey J. Cook, Omar M. Shaikh, Suresh Srinivas
-
Patent number: 9916164Abstract: Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.Type: GrantFiled: June 11, 2015Date of Patent: March 13, 2018Assignee: Intel CorporationInventors: Vineeth Mekkat, Girish Venkatasubramanian, Howard H. Chen
-
Publication number: 20180060049Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: ApplicationFiled: June 6, 2017Publication date: March 1, 2018Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
-
Patent number: 9904546Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.Type: GrantFiled: June 25, 2015Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Jayesh Iyer, Jamison D. Collins, Sebastian Winkel, Howard H. Chen
-
Patent number: 9672019Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: GrantFiled: December 25, 2010Date of Patent: June 6, 2017Assignee: Intel CorporationInventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
-
Publication number: 20160378472Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: Jayesh Iyer, Jamison D. Collins, Sebastian Winkel, Howard H. Chen
-
Publication number: 20160364240Abstract: Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Vineeth Mekkat, Girish Venkatasubramanian, Howard H. Chen
-
Publication number: 20160179538Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: JAMISON D. COLLINS, Jayesh Iyer, Sebastian Winkel, Polychronis Xekalakis, Howard H. Chen, Rupert Brauch
-
Patent number: 8598641Abstract: A semiconductor device and a method of fabricating a semiconductor device, wherein the method includes forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.Type: GrantFiled: November 2, 2011Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung
-
Patent number: 8416121Abstract: A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.Type: GrantFiled: December 8, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Howard H. Chen, Kai D. Feng, Duixian Liu
-
Patent number: 8351166Abstract: A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.Type: GrantFiled: July 24, 2009Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Howard H. Chen, Kai D. Feng, Louis L. Hsu, Seongwon Kim
-
Publication number: 20120146845Abstract: A frequency modulation continuous wave (FMCW) system includes a first memory receiving a clock signal and storing voltage digital values of I FMCW signals, a second memory receiving the clock signal and storing the voltage digital values of the Q FMCW signals, a first digital-to-analog converter (DAC) connected to the first memory and receiving the clock signal for converting the voltage digital values of the I FMCW signal to a first analog voltage, a second digital-to-analog converter (DAC) connected to the second memory and receiving the clock signal for converting the voltage digital values of the Q FMCW signal to a second analog voltage, an I low-pass filter connected to the first DAC smoothing the I FMCW signal and a Q low-pass filter connected to the second DAC smoothing the Q FMCW signal.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Howard H. Chen, Kai D. Feng, Duixian Liu
-
Patent number: 8189419Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.Type: GrantFiled: July 6, 2009Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Howard H. Chen, John A. Fifield, Louis C. Hsu
-
Patent number: 8138085Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.Type: GrantFiled: April 25, 2011Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
-
Publication number: 20120043597Abstract: A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device.Type: ApplicationFiled: November 2, 2011Publication date: February 23, 2012Applicant: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung
-
Patent number: 8086988Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.Type: GrantFiled: May 18, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Nathan Buck, Howard H. Chen, James P. Eckhardt, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Susan K. Lichtensteiger, Chandramouli Visweswariah, Tad J. Wilder
-
Patent number: 8076190Abstract: A semiconductor device and a method of fabricating a semiconductor device is disclosed, the method comprises including: forming etching an oxide layer to form a pattern of parallel oxide bars on a substrate; forming nitride spacers on side walls of the parallel oxide bars, with gaps remaining between adjacent nitride spacers; forming silicon pillars in the gaps; removing the nitride spacers to form a plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film.Type: GrantFiled: August 4, 2009Date of Patent: December 13, 2011Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung
-
Publication number: 20110201199Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.Type: ApplicationFiled: April 25, 2011Publication date: August 18, 2011Applicant: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
-
Publication number: 20110167416Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.Type: ApplicationFiled: December 25, 2010Publication date: July 7, 2011Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
-
Patent number: 7947599Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.Type: GrantFiled: January 23, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott