Patents by Inventor Howard H. Chen
Howard H. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110019321Abstract: A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Applicant: International Business Machines CorporationInventors: Howard H. Chen, Kai D. Feng, Louis L. Hsu, Seongwon Kim
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Publication number: 20110002188Abstract: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.Type: ApplicationFiled: July 6, 2009Publication date: January 6, 2011Applicant: International Business Machines CorporationInventors: Howard H. Chen, John A. Fifield, Louis C. Hsu
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Publication number: 20100293512Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.Type: ApplicationFiled: May 18, 2009Publication date: November 18, 2010Applicant: International Business Machines CorporationInventors: Nathan Buck, Howard H. Chen, James P. Eckhardt, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Susan K. Lichtensteiger, Chandramouli Visweswariah, Tad J. Wilder
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Patent number: 7675789Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.Type: GrantFiled: June 6, 2008Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H. K. Tang
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Publication number: 20090309136Abstract: A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.Type: ApplicationFiled: August 4, 2009Publication date: December 17, 2009Applicant: International Business Machines CorporationInventors: Howard H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung
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Publication number: 20090184264Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.Type: ApplicationFiled: January 23, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
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Patent number: 7499308Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.Type: GrantFiled: March 21, 2007Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H. K. Tang
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Publication number: 20080273393Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.Type: ApplicationFiled: March 21, 2007Publication date: November 6, 2008Inventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H. K. Tang
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Publication number: 20080266984Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.Type: ApplicationFiled: June 6, 2008Publication date: October 30, 2008Applicant: International Business Machines CorporationInventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H.K. Tang
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Patent number: 6910165Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.Type: GrantFiled: February 28, 2001Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Howard H. Chen, Li-Kong Wang, Louis L. Hsu, Sang H. Dhong, Tin-chee Lo
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Patent number: 6825534Abstract: A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.Type: GrantFiled: December 27, 2000Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang
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Patent number: 6823293Abstract: A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.Type: GrantFiled: December 31, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis Lu-Chen Hsu, Brian L. Ji, Li-Kong Wang
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Publication number: 20040128115Abstract: A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system comprises a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Applicant: International Business Machines CorporationInventors: Howard H. Chen, Louis Lu-Chen Hsu, Brian L. Ji, Li-Kong Wang
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Patent number: 6728916Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.Type: GrantFiled: May 23, 2001Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang
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Publication number: 20020178416Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: IBM CorporationInventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang
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Publication number: 20020120898Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.Type: ApplicationFiled: February 28, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporatonInventors: Howard H. Chen, Li-Kong Wang, Louis L. Hsu, Sang H. Dhong, Tin-chee Lo
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Publication number: 20010016383Abstract: A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.Type: ApplicationFiled: December 27, 2000Publication date: August 23, 2001Inventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang
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Patent number: 6214653Abstract: A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.Type: GrantFiled: June 4, 1999Date of Patent: April 10, 2001Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang