Patents by Inventor Howard R. Test
Howard R. Test has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535104Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.Type: GrantFiled: April 11, 2007Date of Patent: May 19, 2009Assignee: Texas Instruments IncorporatedInventors: Howard R Test, Donald C Abbott
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Publication number: 20080274294Abstract: A metal structure (100) for a contact pad of a semiconductor device, which has interconnecting traces of a first copper layer (102). The substrate is protected by an insulating overcoat (104). In the structure, the first copper layer of first thickness and first crystallite size is selectively exposed by a window (110) in the insulating overcoat. A layer of second copper (105) of second thickness covers conformally the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The second thickness is selected so that the distance a void from the second layer can migrate during the life expectancy of the structure is smaller than the combined thicknesses of the first and second layers. A layer of nickel (106) is on the second copper layer, and a layer of noble metal (107) is on the nickel layer.Type: ApplicationFiled: July 18, 2008Publication date: November 6, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Howard R. Test, Donald C. Abbott
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Patent number: 7413974Abstract: A metal structure (100) for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer (102). The substrate is protected by an insulating overcoat (104). The first copper layer of first thickness and first crystallite size is selectively exposed by a window (110) in the insulating overcoat. A second copper layer (105) of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer (106) is on the second copper layer, and a noble metal layer (107) is on the nickel layer.Type: GrantFiled: August 4, 2005Date of Patent: August 19, 2008Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Donald C. Abbott
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Publication number: 20080157300Abstract: Methods for assembling thermally enhanced semiconductor device packages are disclosed in which a chip assembly has a chip affixed to a leadframe. A thermal pad is affixed to a surface of the chip, and the chip assembly is encapsulated whereby a surface of the thermal pad remains exposed to form at least a portion of a surface of the package favorable for the egress of heat from the chip. Also disclosed are thermally enhanced semiconductor device packages made using the methods of the invention.Type: ApplicationFiled: February 8, 2007Publication date: July 3, 2008Inventors: Shih-Fang Chuang, Howard R. Test
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Patent number: 7265443Abstract: A semiconductor device has a semiconductor chip with a periphery and an IC organized in a core portion and a peripheral portion. The IC has a top level of interconnecting metal traces (510) from the peripheral portion to the core portion; the traces are covered by an insulating overcoat (520) which has peripheral windows to expose bond pads. The circuit further has at least one level of metal lines (511) on top of the insulating overcoat; the lines lead from the chip periphery towards the chip core, wherein each line (511) is substantially parallel to one of the traces (510) underneath the insulating overcoat and vertically aligned therewith. After assembling the chip onto a leadframe with segments (504), bonding wires (502) connect the bond pads (510a) and the metal lines (511a) with the segments.Type: GrantFiled: April 29, 2005Date of Patent: September 4, 2007Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Michael A. Lamson
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Patent number: 7217656Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.Type: GrantFiled: May 31, 2005Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Donald C. Abbott
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Patent number: 6869875Abstract: An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.Type: GrantFiled: August 6, 2003Date of Patent: March 22, 2005Assignee: Texas Instruments IncorporatedInventor: Howard R. Test
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Patent number: 6800555Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.Type: GrantFiled: March 23, 2001Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Gonzalo Amador, Willmar E. Subido
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Publication number: 20040084511Abstract: An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.Type: ApplicationFiled: August 6, 2003Publication date: May 6, 2004Inventor: Howard R. Test
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Publication number: 20040018675Abstract: A flexible plating method by continuously controlling the hydrogen concentration of the plating bath by adding controlled amounts of hydrogen gas. The control of the hydrogen concentration is provided by selected distribution and number of nozzles and size of orifices; and predetermined pressure and duration of hydrogen gas flowing through the nozzles, wherein pressure and duration may be variable with time.Type: ApplicationFiled: July 1, 2003Publication date: January 29, 2004Inventors: Howard R. Test, Homer B. Klonis
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Patent number: 6619538Abstract: A flexible plating method by continuously controlling the hydrogen concentration of the plating bath by adding controlled amounts of hydrogen gas. The control of the hydrogen concentration is provided by selected distribution and number of nozzles and size of orifices; and predetermined pressure and duration of hydrogen gas flowing through the nozzles, wherein pressure and duration may be variable with time. The control of the hydrogen concentration is selected to provide a ramp-up phase, needed for a rapid plating start, followed by a saturation phase, for consistent plating stability. With metal layer plating under control, a robust, reliable and low-cost metal structure enabling electrical wire connections to the interconnecting copper metallization of ICs is formed. The structure comprises a layer of barrier metal, preferably nickel, that resists copper diffusion, deposited on the non-oxidized copper surface.Type: GrantFiled: May 2, 2002Date of Patent: September 16, 2003Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Homer B. Klonis
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Patent number: 6616967Abstract: An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.Type: GrantFiled: April 15, 2002Date of Patent: September 9, 2003Assignee: Texas Instruments IncorporatedInventor: Howard R. Test
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Publication number: 20030107137Abstract: A microelectronic mechanical structure (MEMS) comprising a semiconductor chip having an integrated circuit including a plurality of micromechanical components, and a plurality of conductive routing lines integral with the chip; the routing lines having contact terminals of oxide-free metal; and the terminals having a layer of barrier metal on the oxide-free metal and an outermost layer of noble metal, whereby damage-free testing of the circuit is possible using test probe needles.Type: ApplicationFiled: September 24, 2001Publication date: June 12, 2003Inventors: Roger J. Stierman, Seth Miller, Howard R. Test, Christo P. Bojkov, John P. Harris, Reynaldo M. Rincon, Scott W. Mitchell, Gonzalo Amador
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Publication number: 20030071319Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 &mgr;m. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm2/s at 250° C. and a thickness of less than 1.5 &mgr;m. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.Type: ApplicationFiled: July 12, 2002Publication date: April 17, 2003Inventors: Roger J. Stierman, Gonzalo Amador, Howard R. Test
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Publication number: 20010035452Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection.Type: ApplicationFiled: March 23, 2001Publication date: November 1, 2001Inventors: Howard R. Test, Gonzalo Amador, Willmar E. Subido
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Publication number: 20010033020Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 &mgr;m. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm2/s at 250° C. and a thickness of less than 1.5 &mgr;m. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.Type: ApplicationFiled: February 1, 2001Publication date: October 25, 2001Inventors: Roger J. Stierman, Gonzalo Amador, Howard R. Test
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Patent number: 6268662Abstract: A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment materiaType: GrantFiled: October 14, 1999Date of Patent: July 31, 2001Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Wei-Yan Shih, Willmar Subido
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Patent number: 6068180Abstract: A system (270, 370) for connecting a semiconductor chip (22, 322) to a leadframe (12), the system (270, 370) includes a three-dimensional leadframe (12) and a bonding support mechanism (202, 302, 402). The leadframe (12) may include a first lead (32, 132, 332, 432) having a first base portion (144), a first lead tip (42, 142, 342, 442), and a first longitudinal axis (305); a second lead (30, 130, 330, 430) having a second base portion (140, 321), a second lead tip (36, 136, 336, 436), and a second longitudinal axis. The first lead (32, 132, 332, 432) and second lead (30, 130, 330, 430) formed substantially adjacent to each other, and the second lead (30, 130, 330, 430) having a stepped portion (38, 138, 338, 438) such that the lead tips (42, 142, 342, 442, 36, 136, 336, 436) of the first lead (132, 332, 432) and second lead (130, 330, 430) are separated in a Z-direction (52) and in a Y-direction (52).Type: GrantFiled: December 16, 1997Date of Patent: May 30, 2000Assignee: Texas Instruments IncorporatedInventor: Howard R. Test
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Patent number: 5979743Abstract: A method of using a single-headed bonder (80) to form bonds to bond pads (16) is provided. A single-headed bonder (80) includes a capillary (22) having a capillary face (40) with a long dimension along a first axis (BB) and a short dimension along a second axis (CC). The long dimension of the capillary face (40) is aligned in a first orientation such that the bond pads (16) are bonded in a first direction associated with the first orientation. The capillary (22) is then rotated to place the long dimension in a second orientation such that all the bond pads (16) are bonded in a second direction associated with the second orientation. In place of rotating the capillary (22), a second single-headed bonder (90) having a capillary (22) rotated to the second orientation can be used to bond bond pads (16) in the second direction. Transportation between bonders can be done manually, by a transport mechanism (60), by a robotic arm (70), or other suitable means.Type: GrantFiled: May 29, 1997Date of Patent: November 9, 1999Assignee: Texas Instruments IncorporatedInventor: Howard R. Test
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Patent number: 5544804Abstract: A capillary tube (1) for bonding wire (5) has a bore (3) and a cross section in a direction normal to the bore having a long dimension and a short dimension in a direction normal to the long dimension. The bond is made to bond pads (9) using the capillary tube by bonding a wire to one bond pad while the capillary is oriented with the long dimension (25 to 27 or 35 to 37) in a first direction and bonding a wire to a die immediately adjacent the one bond pad with the capillary which can be oriented with the long dimension in the same direction or in a direction normal to the first direction, as may be required.Type: GrantFiled: June 8, 1994Date of Patent: August 13, 1996Assignee: Texas Instruments IncorporatedInventors: Howard R. Test, Michael R. Vinson, Albert H. Kuckhahn