Abstract: According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits.

Abstract: In accordance with the present description, provided are hierarchical and parallel partition networks which include a plurality of parallel partition packet networks for interconnecting components on one or more integrated circuit dies. In one embodiment, each parallel partition packet network is independent of the other parallel partition packet networks and has a unit level switch at a unit hierarchical level. In another aspect, each parallel partition packet network has a unit-to-unit level switch at a unit-to-unit hierarchical level. Other aspects are described herein.

Abstract: According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits.

Abstract: In one embodiment, the present invention includes a power manager to receive a memory power usage value, to determine an available power based at least in part on a power budget and the memory power usage value, and to change a memory power state based at least in part on the available power, wherein the memory power state comprises a memory frequency and a memory voltage. Other embodiments are described and claimed.

Abstract: A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Abstract: A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Abstract: Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.

Abstract: Memory power estimation by means of calibrated weights and activity counters are generally presented. In this regard, in one embodiment, a memory power is introduced to read a value from a memory activity counter, to determine a memory power estimation based at least in part on the value and a calibration, and to store the memory power estimation to a register. Other embodiments are also described and claimed.

Abstract: A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Abstract: Methods and apparatuses for adaptive memory operational state management. A memory performance parameter is determined for at least a portion of a memory system. The memory performance parameter is compared to one or more threshold values. An operating frequency of the memory system can be modified based on results of the comparison of the memory performance parameter and the one or more threshold values.

Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract: In one embodiment, the present invention includes a power manager to receive a memory power usage value, to determine an available power based at least in part on a power budget and the memory power usage value, and to change a memory power state based at least in part on the available power, wherein the memory power state comprises a memory frequency and a memory voltage. Other embodiments are described and claimed.

Abstract: Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.

Abstract: Methods and apparatuses for adaptive memory operational state management. A memory performance parameter is determined for at least a portion of a memory system. The memory performance parameter is compared to one or more threshold values. An operating frequency of the memory system can be modified based on results of the comparison of the memory performance parameter and the one or more threshold values.

Abstract: Memory power estimation by means of calibrated weights and activity counters are generally presented. In this regard, in one embodiment, a memory power is introduced to read a value from a memory activity counter, to determine a memory power estimation based at least in part on the value and a calibration, and to store the memory power estimation to a register. Other embodiments are also described and claimed.

Abstract: A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method also includes programming a second ODT value into a second plurality of additional DRAM devices. The second plurality of additional DRAM devices are also located on the DIMM. The method also specifies that the first and second ODT values are not the same value.

Abstract: A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

Abstract: In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency.

Abstract: In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency. Other embodiments are described and claimed.

Abstract: A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method also includes programming a second ODT value into a second plurality of additional DRAM devices. The second plurality of additional DRAM devices are also located on the DIMM. The method also specifies that the first and second ODT values are not the same value.