Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract: A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second implementation the command precharges one quarter of the banks. The power drawn by the upper or lower bank precharge on the eight bank DRAM is the same as the power drawn by an “all bank” precharge on a four bank DRAM, without requiring the precharge period to be extended.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. Writes to a memory module are stored in the data cache which allows the writes to be postponed until the DRAM on the memory module is not busy.

Abstract: Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates a set of data transfer operations to transfer data between the data bus and one of the one or more memory devices; and a timing unit, coupled to the one or more memory devices, to receive the command signal, a flag signal, and a memory select signal, the timing unit to generate a trigger signal, in response to a transition of the flag signal, to complete the data transfer operations if the memory select signal corresponds to the one of the one or more memory devices. Other embodiments have been claimed and described.

Abstract: An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The memory controller communicates with the memory module via a variety of commands. Included in these commands are an activate command and a cache fetch command. A command is delivered from the memory controller to the memory modules over four transfer periods. The activate command and the cache fetch command have formats that differ only in the information delivered in the fourth transfer period. A read command and a read and preload command similarly differ only in the information delivered over the fourth transfer period.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. One intended advantage of this example embodiment is the ability to read a current line of data out of a memory module DRAM and to load the next cache line of data into the memory module data cache. This allows the utilization of excess DRAM interconnect bandwidth while preserving limited memory bus bandwidth.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The tag look-ups are performed in parallel with the memory module decodes. This improves latency for cache hits without penalizing the latency for cache misses.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. This embodiment includes an option to segment the cache. When the cache is segmented, the cache line size is halved. The segmentation allows the entire cache to be accessed without doubling the amount of tag address storage locations. The non-segmented cache may be used for memory systems using a burst length of eight bytes, while the segmented cache may be used for memory systems using a burst length of four bytes.

Abstract: A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Abstract: In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.

Abstract: A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable this data trigger scheme to work even in heavily loaded configurations where there is more timing skew.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable the data trigger scheme to work in a more heavily loaded configuration where there is more timing skew.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The memory controller communicates with the memory module via a variety of commands. Included in these commands are an activate command and a cache fetch command. A command is delivered from the memory controller to the memory modules over four transfer periods. The activate command and the cache fetch command have formats that differ only in the information delivered in the fourth transfer period. A read command and a read and preload command similarly differ only in the information delivered over the fourth transfer period.