Patents by Inventor Hsi-Chia Chang

Hsi-Chia Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7363552
    Abstract: The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 22, 2008
    Assignee: Mediatek Inc.
    Inventors: Wei-Hung Huang, Hsi-Chia Chang, Ching-Chieh Wang
  • Publication number: 20080022192
    Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
    Type: Application
    Filed: September 27, 2007
    Publication date: January 24, 2008
    Inventors: Yi-Kwang Hu, Jin-Bin Yang, Hsi-Chia Chang
  • Publication number: 20050262415
    Abstract: The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.
    Type: Application
    Filed: May 18, 2005
    Publication date: November 24, 2005
    Inventors: Wei-Hung Huang, Hsi-Chia Chang, Ching-Chieh Wang
  • Publication number: 20050177781
    Abstract: A two-dimensional array is stored in a first storage memory. A data accessing direction of the first storage memory is in a row direction. A method for reading data in the two-dimensional array in a column direction contains reading a plurality of data sets in the array from the first storage memory; performing a calculating operation on a first data set of the plurality of data sets; storing remaining data sets of the plurality of data sets into a second storage memory; and sequentially reading and applying the calculating operation on the remaining data sets stored in the second storage memory.
    Type: Application
    Filed: November 3, 2004
    Publication date: August 11, 2005
    Inventors: Hsi-Chia Chang, Chin-Huo Chu
  • Publication number: 20050120285
    Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
    Type: Application
    Filed: October 22, 2004
    Publication date: June 2, 2005
    Inventors: Yi-Kwang Hu, Jin-Bin Yang, Hsi-Chia Chang