Patents by Inventor Hsi-Kuei Cheng

Hsi-Kuei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030016
    Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu
  • Patent number: 7026233
    Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: April 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Hung-Ju Chien, Hsun-Chang Chan, Chu-Chang Chen, Ying-Lang Wang, Chin-Hao Su, Hsien-Ping Feng, Shih-Tzung Chang
  • Patent number: 6985222
    Abstract: A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: January 10, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Chu-Chang Chen, Ting-Chun Wang, Szu-An Wu, Ying-Lang Wang, Hsien-Ping Feng
  • Publication number: 20050239221
    Abstract: A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 27, 2005
    Inventors: Hsien-Ping Feng, Min-Yuan Cheng, Hsi-Kuei Cheng, Steven Lin, Huang-Yi Huang, Yuh-Da Fan
  • Publication number: 20050227479
    Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 13, 2005
    Inventors: Hsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu
  • Patent number: 6863491
    Abstract: A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: March 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsi-Kuei Cheng, Chun-Tse Lin, Ting-Chun Wang, Yu-Ku Lin, Ying-Lang Wang
  • Publication number: 20050032353
    Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 10, 2005
    Inventors: Hsi-Kuei Cheng, Hung-Ju Chien, Hsun-Chang Chan, Chu-Chang Chen, Ying-Lang Wang, Chin-Hao Su, Hsien-Ping Feng, Shih-Tzung Chang
  • Publication number: 20040212798
    Abstract: A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.
    Type: Application
    Filed: April 25, 2003
    Publication date: October 28, 2004
    Inventors: Hsi-Kuei Cheng, Chu-Chang Chen, Ting-Chun Wang, Szu-An Wu, Ying-Lang Wang, Hsien-Ping Feng
  • Publication number: 20040131460
    Abstract: A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 8, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Kuei Cheng, Chun-Tse Lin, Ting-Chun Wang, Yu-Ku Lin, Ying-Lang Wang
  • Patent number: 6695921
    Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: February 24, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Kuei Cheng, Ting-Chu Wang, Yu-Ku Lin, Chin-Te Huang, Huai-Tei Yang, Chun-Chang Chen, Yi-Lang Wang
  • Publication number: 20030230237
    Abstract: An improved hoop support for semiconductor wafers reduces contamination of the wafer during edge beveling operations through the use of support pins that make only line contact with the wafer. The support pins are spaced around the periphery of the hoop and possess a triangular cross section. Two intersecting sides of the pins form an edge that defines the line contact with the wafer. These intersecting sides are preferably inclined relative to the wafer at an angle of between 60 and 80 degrees.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 18, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Kuei Cheng, Ting-Chu Wang, Yu-Ku Lin, Chin-Te Huang, Huai-Tei Yang, Chun-Chang Chen, Yi-Lang Wang
  • Patent number: 6585826
    Abstract: A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: July 1, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yali Tai, Shih-Chi Lin, Wen-Long Lee, Francis Wang, Szu-An Wu, Hsi-Kuei Cheng, Ying-Lang Wang
  • Publication number: 20030084919
    Abstract: A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to the at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.
    Type: Application
    Filed: November 2, 2001
    Publication date: May 8, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yali Tai, Shih-Chi Lin, Wen-Long Lee, Francis Wang, Szu-An Wu, Hsi-Kuei Cheng, Ying-Lang Wang
  • Publication number: 20020194790
    Abstract: A method for fabricating diamond conditioning disc and the disc fabricated are described. In the method, a substrate for a diamond conditioning disc is first provided, a layer of a binder material such as an alloy of nickel is then coated on top of the diamond conditioning disc, a plurality of diamond particles is then implanted in a layer of binder material such that not more than ⅔ of a diameter, or of a height of the multiplicity of diamond particles is exposed above a top surface of the layer of the binder material. In a preferred embodiment, the multiplicity of diamond particles is implanted in a layer of binder material such that between about ½ and about ⅔ of a diameter, or of a height of the particles is exposed, or protruded above a top surface of the binder material layer.
    Type: Application
    Filed: June 21, 2001
    Publication date: December 26, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,
    Inventors: Ting-Chun Wang, Hsi-Kuei Cheng, Yu-Ku Lin, Yi-Lang Wang
  • Patent number: 6482290
    Abstract: A sweeping slurry dispensing device for use in a chemical mechanical polishing apparatus for the uniform distribution of a slurry solution on top of a polishing pad is described. The sweeping slurry dispensing device consists of a drive wheel, a dispenser wheel, a push arm, a motor means and a slurry dispensing nozzle. A first end of the push arm is pivotally attached to the outer periphery of the dispenser wheel while a distal second end equipped with a roller for rollingly engaging in outer surface of the oval-shaped drive wheel. The slurry dispensing nozzle is attached to a bottom surface of the drive wheel for dispensing the slurry solution in an arcuate path when the dispenser wheel is turned by the drive wheel.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: November 19, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsi-Kuei Cheng, Yi-Wei Chang, Li-Hsiao Chao, Tzut Hsun Huang